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reading image file in verilog

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nids

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Hi,

i have one text file which is the output of unsigned value of character of one .raw image file.
can you please tell me which function can i use to read that file?
i used "readmemh" but its only for hex value but i have unsigned character value.
please tell me how can i proceed to read that file?

Thnks,
 

Hey,


so what is wrong with that..
What is the size of your file. What is the size of data.
In the following case I assume that size of file is 256 and the size of each data is 8bits

follow this code

Code: 
module test(clk , dataout);
input clk;
output reg [7:0] dataout;

reg [7:0] memory [255:0] //memory
integer i =0; 

initial $readmemb("imagefile.txt",memory );
//$readmemh for hex
//This way you have stored your file data into the memory in binary format;
//
//Now if you want to read from memory..


always@(posedge clk)  

if(i <256) begin
 dataout <= memory[i]
 i <= i + 1;
end


endmodule

But be sure that this memory is not synthesizable. To make the synthesizable code you need to store these values in ROM

Hope this works
bests,
Shan
 
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    nids

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Hi

So I think your memory size should be 352*288 but the size of the each word is different, in the example above it is 1 Byte.

Bests,
Shan -no sir :)
 
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    nids

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No need to worry about that, since the FPGA deals in binary only even if you have char, real or any thing.

Also I did not find any attached file.

Bests,
Shan
 
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    nids

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Well I cannot understand this file...

What is your actual data file, can you send that one.
Since this file seems to be some other format transformed into text
 
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    nids

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Well in my opnion you should first use matlab to convert you image file into some real number format, then you should save it in .txt format and read using the program discussed earlier

Have you converted your image file into text file.

You should try and convert image into suitable format first

Bests,
Shan
 
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Hi

First of all never use blocking statement in synchronous system (i.e. like @posedge clk)

always@(posedge clk)
dataout <= memory;

also the memory is just 1D array

Code: 
int i =0;
always@(posedge clk )
begin
if (reset == 1'b1)
    dataout <= 8'b0;

else
if(i < `height * `width)
begin
      dataout <= memory[i];
      i <= i +1;
end

else dataout <= 8'b0;

why you use for loop inside the @posedge, this way the loop be processed after the first clock edge and will finish as well.

Also how you make the image file I am not sure, but I think two hex numbers should represent 1 pixel, so as you will store in the memory...

Also I suggest do some more reading for verilog and HDL language, no hard feelings, I also am in learning phase but learn by doing... :)

Always welcome to ask.


Shan

- - - Updated - - -

nids said:
hi,

thanks shaan :)
in my case 1 pixel represents 1 hex number because number of pixels that is (352*288 = 101376) is equal to 101376 hex number so i assume that it should be like that only..what say?

thanks,
Click to expand...

Well, I doubt that, since 1 hex = 4 bits, while usually an image is represented by at least 1 Byte. so I guess that that it is 101376 Bytes, do not assume. Do some work over it. Unless you are not sure of the lenghts of bits etc. while dealing with FPGAs, it will be difficult for you.

I repeat, never assume, be definite.

Bests,
Shan
 
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yes u r true :)
i never think like that

so can you please tell me what can i do for that?
 

Sorry for late reply,

Well now all you need to do is to store the data in the memory by the method you have already tried, the width of memory should be 8 bits if your pixel is 8 bit and the depth of memory is 352*288

I think you should try and then you will learn more this way.
The more you try, the easier things get.

Bests,
Shan
 

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