concept regarding Buried layer

hi all
How buried layer reduce latch up effect in nmos explain in brief ? dont say tht resistance decrease and latch up will reduce


Thanks and regareds
Kishan.B

In recent years, improved technology has made it possible to combine complimentary MOS transistors and bipolar devices in a single process at a reasonable cost.
A single n-epitaxial layer is used to implement both the PMOS transistors and bipolar npn transistors.

Its resistivity is chosen so that it can support both devices. An n+ - buried layer is deposited below the epitaxial
layer to reduce the collector resistance of the bipolar device, which simultaneously increases the immunity to latchup.

The p-buried layer improves the packing density, because the collector-collector spacing of the bipolar devices can be reduced.
It comes at the expense of an increased collector-substrate capacitance.

If you look at a CMOS cross section (or the more complex BiCMOS cross section shown above), you have the following pnpn structure:

PMOS p+ drain/source
n well
p substrate
NMOS n+ drain/source

which gives you a parasitic pnp and a parasitic npn transistor, cross coupled in a feedback loop. Under normal conditions, all pn junctions are biased in reverse direction. If the gains of both parasitic (pnp and npn) transistors are high enough and you have some current injection, e.g. by pulses on the power supply or a pulse below substrate zero voltage at the input, this current is amplified by on bip, injected into the base of the second bip, amplified, again injected into the base of the first and so on and so on, and thus an avalanche, aka latch up occurs.

If you use an n+ buried layer, the 'base doping' of the parasitic pnp is increased substantially, resulting in a reduced gain of this transistor. So the effect of the feedback is reduced. The buried layser's low resistance also serves to lead injected currents to the power supply terminal, so they may no longer be amplified, again reducing danger of latchup. Both phenomena, plus the same with a p+ burid layer on the NMOS side, will suppress latchup.