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[SOLVED] Buffers timing delay issue

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LaxmiNarayanan

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Why are the buffers inserted to reduce timing delay in a cts ? Buffers add to delay , right ? Please explain .
Also we add cascaded buffers , like if d is drive strength , the buffers drive strength varies as d , ad , a²d ,a³d ......... Why is this done ? How does it help in timing optimization ?
 

Buffers do add delay to the Circuitry. But they are essentially added in order to strengthen the net and maintain stronger logic value by acting as current amplifiers.

For suppose if there are varying delays in a H-tree Clock distribution network i.e clock skew, these buffers placed along every net equalizes the net delay in all the paths.

SO they do eliminate the CLock Skew.

Varying of buffer strength like ad, a^2d etc.. is done usually in the cascading of inverters. This is done to effectively reduce the input coupling capacitance of the next stage w.r.t previous stage so that the propagation delays(RC delays) are well managed.
 
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