when and why to set_disable_timing?

set_disable_timing

hi members, I am puzzled about when and why to set_disable_timing or set_false_path. For example,here is a figure in the book" advanced asis chip synthesis(2nd)".
the author suggests that we should use dc_shell command :
set_disable_timing U1 -from A -to Z
to disable the delay calculation for Pin A to Pin Z of cell U1.
And my question is : why not to calculating the delay?

thanks.

set_disable_timing set_false_path

I think you should explain more about the circuit and conditions. It depends on which delays are computing. If you want to compute the delay of Z=1, when signal_a is set to 0, you do not need to compute propagation delay of reset signal.

Regards,
KH

set_disable_timing example

because the A point, which is a reset signal, is not a switching signal in normal operation of this circuit.
so it's not needed to take the delay from A to Z in account. Sometimes if the delay from A to Z is shorter than the delay from B to Z, you can ignore it.

difference false_path set_disable_timing

I think, in this figure, input A of NAND gate isn't function path, so disable this path from timing report.
Is it right???

set_disable_timing usage

First, the difference between set_false_path and set_disable_timing commands:
set_false_path command will remove all timing constraints from the path. Tools still calculate the path delay, but don't report it to be an error. While set_disable_timing will remove paths from timing analysis. So you can see set_disable_timing is more efficient than set_false_path command.

Second, in the example circuit, U1/A is a reset signal, which has no timing requirement and has a large delay to U1/Z. The transition time of U2 is affected by the cell delay of U1, which is calculated on the largest timing path, that is U1/A to U1/Z. So if not disable it, the cell delay of U2 will be much bigger than actual. The false error may hide the real violation.