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Clock Recovery Circuit by FPGA

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davyzhu

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Hello all,

I tried to design a digital PLL to recover the clock from input data,
it consists of FPGA, and a VCO.

I find two ways to control the VCO by FPGA in analog way.
1) FPGA output PWM --> RC Low-pass filter --> VCO --> return to FPGA
2) FPGA --> D/A --> VCO --> return to FPGA

BTW, how to choose a D/A for such design, should I compare which parameter? And is 10 MSPS be quick?

Do you think which one is better and do you have better way to implement it?

Regards,

Davy Zhu
 

It depends on your requirement,
RC loww-pass filter is easy to implement
(cheaper), but you will have spurs
on your VCO control line, which may result
for example as adjascent channel leakage.
For D/A you have to check the following
1. Your control of the VCO will be in discrete
domain. This will introduce an extra phase shift
in your loop. So you have to be very careful with
the stability of the pll. You have to consider the bandwidth of the pll together with the phase shift due to discrete time control.
2. At the output of the DA also you have to put
an RC low pass filter
 

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    davyzhu

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