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If you mean "In phase" , you can generate the three clocks above with a single MMCM driven by a single input clock. The three output clocks will be related and timing constraints will be automatically generated on the output clocks if a timing constraint exist on the input.
I will explain:
i need to generate number of clock s with a help of 555 1)supposed to be 625 hz 2) supposed to be 2.5khz .I was trying to generate them and i did it but they had time sheft between them so i tried to enter the fast one to dfliplop as clock and slow one to D but still same problem.
Please help.
Thx
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