[SOLVED] Differential amplifier for current sense noise problems (schematic)

Hello,

I have designed a low side current sense amplifier. Since there are high currents in the circuit, differential current sensing is preferred to avoid common mode noise. However, the circuit I designed does not attenuate common mode signals as I would expect. Since high speed is needed for short-circuit detection the step response of the circuit should not exceed 3 µs. High accuracy is not needed, only a good trade-off between response time, proper filtering and gain.

I attach the simplified circuit (supply filter, proper routing issues have been taken into account). Resistors are 0.1% for best CMRR and capacitors NPO. Is placing a 3.3 nF capacitor at the amplifier input a mistake? Are the CM 10 pF capacitors propperly placed? If capacitors are not "matched" may this amplify common mode noise?

Thank you for your comments and suggestions.

Ernest

What package are you using for the op amp since I seen none in the data sheet that have the pinout you are using?

Any capacitor or resistor mismatch will cause amplification of common-mode signals.

Hi.

Because of the fact that a pair of resistors and capacitor won't have excactly the same values in real life, the filters on the input will slightly differs from each other.

Therefore I'll claim that the circuit is very sensible for small variations (or errors if you want) in RC values.

I haven't read the datasheet for the opamp before posting so that leaves a posibillity that the filter is faster than the opamp. Faster opamp will make it more sensible to RC deviations.

The worst point is that the 3.3 nF capacitor makes the feedback loop instable. You get most likely continuous oscillations of 0.3 - 0.5 MHz.

The pinout has been extracted from the manufacturer PSPICE model and does not match the real component pinout. The footprint is SOT-23-5. Is there another configuration that reduces this RC tolerance issues like placing capacitor in parallel to R4?

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FvM,
do you suggest adding resistors in series with inverting and non inverting inputs (between opamp IC and circuit) to mitigate this instability?

As FvM noted, you need to remove C1 and also C3. You never want to intentionally add capacitance to the summing junction of an op amp, since it can cause instability and ringing in the circuit response.

If you want to filter noise, then add a capacitor across R4. But the capacitance tolerance difference between that capacitor and C2 will still degrade the common-mode rejection.

If you really need high common-mode rejection (greater than about 40dB) then use an integrated circuit instrumentation or differential amp designed specifically for that purpose. They have closely matched internal components to give a high CMRR.

do you suggest adding resistors in series with inverting and non inverting inputs (between opamp IC and circuit) to mitigate this instability?

Click to expand...

I didn't suggest a specific circuit, just reminded amplifier stability requirements. But yes, series resistors between input capacitor and feedback summing points can solve the problem. Check the loop gain phase margin.

Thank you for your comments, changing the capacitor position and using NPO ones (5%) improves CMRR to an acceptable level.