FPGA clock gating - does it save any power ?

Can clock gating ( in code ) save power with FPGA devices ?

shaiko said:

Can clock gating ( in code ) save power with FPGA devices ?

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It can, but in many cases it will not. A possible application where it might is one where the gated clocks are just not running at all for long periods. I did an evaluation of a gated clock versus free running clock implemenation of the same state machine logic and found it to use far more power (several X) and had a slower maximum clock speed. The person I did this for provided the example state machine and a claim that his method of generating the gated clocks targetting an FPGA would use less power and run faster. I disproved both of his claims while targeting brand A and brand X FPGA devices. However, such an example does not prove that gated clocks will never save power, but it does show that it is tough bar to hurdle.

The likely reason that gated clock designs tend to use more power is that the FPGA hardware has a low capacitance clock tree whereas gated clocks will use general routing resources which will tend to have much higher capacitance. The charging and discharging of that capacitance is what leads to power consumption. ASICs don't have such a limitation (they have different ones) which is why gated clocks in custom ASICs generally do save power.

Kevin Jennings