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Signal stop_internal cannot be synthesized, bad synchronous description

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hello.how can I solve it?
I want when the process is started the signal "stop_internal='1' and when it finished signal "stop_internal ='0' ,but this error is occured?
Signal stop_internal cannot be synthesized, bad synchronous description
Code: 
process(clk,reset,clk_external,clr_in)
    variable  i:integer range 0 to 8;
    variable col_index_nonzero_i:integer range 1 to 2304;
    variable a:integer range 0 to 1;
    variable stop_internal:bit;
    begin 
      if reset ='1' then 
        i:=0;
      else
        if (clr_in'event and clr_in='1') then
          stop_internal:='1';
        end if;
         if (clk'event and clk='1')and (stop_internal='1') then 
          if i=length_row then
           i:=1;
           stop_internal:='0';
           i:=1;
          else
            i:=i+1;
          end if;
			    if b>0 then 
            a:=1;
          else
            a:=0;
          end if;
end if;
end if;
end process;
 

Hi,

first of all, could you please post the entire design? Not only the process, but the entity you are describing.

Also, I guess the signal 'clr_in' is like a reset signal, so why do you treat it as a clock? You should use it either as synchronous or asynchronous reset. In addition, the synthesis tool does not like the fact that you are trying to describe two subsequent clocks in the same process (the one with 'clr_in' and the one with 'clk' events), and this is not good.

Try changing your design this way, and the come back to us. Hope this helps you in some way

Cheers
 
kingslayer said:
Hi,

first of all, could you please post the entire design? Not only the process, but the entity you are describing.

Also, I guess the signal 'clr_in' is like a reset signal, so why do you treat it as a clock? You should use it either as synchronous or asynchronous reset. In addition, the synthesis tool does not like the fact that you are trying to describe two subsequent clocks in the same process (the one with 'clr_in' and the one with 'clk' events), and this is not good.
Try changing your design this way, and the come back to us. Hope this helps you in some way

Cheers
Click to expand...

Yes, this is why you are getting the error message. Only one 'event per process.
 
thank you, what am I doing? I want this program to be implemented when the previous program was runned,so I use a signal be '1' when the previous program ended and when this signal event and be '1' the current program run
 

Hi,

I want this program to be implemented when the previous program was runned
Click to expand...

what do you mean by "program"? What do you mean by "this program to be implemented"?
This is not C, nor it is software programming...

What are you modeling really?

Cheers
 
kingslayer said:
Hi,

This is not C, nor it is software programming...


Cheers
Click to expand...
Hi,I khow it,but ...
my program is created from several subprogram that each of subprogram is processed after another .in other ways I need a triiger signal in every subprogram, that comes from previous subprogram ,so that the current subprogram will run only in finite time, to save energy)

I have only this way.and dont know any way.how can I do it ?
 

I think, we should lay the "run program" discussion aside and look for the "bad synchronus description" point in your initial post. Whatever you imagine your code to do, it's simply wrong that there are no other ways to implement an equivalent function in synthesizable VHDL.

You are describing a storage element (DFF) for stop_internal. Like a DFF logic chip (e.g. 7474), it has one clock input, a data input and asynchronous set and rest inputs. But you are trying to design a DFF with two clock inputs clr and clk. That works neither in wiring of logic chips nor FPGA design.

There may be cases where you really need two edge triggers control a single signal. That's no absolutely impossible but needs to combine several DFFs and additional logic. I'm however rather sure, that you don't need it in the present case. You rarely need to implement clr as an edge sensitive signal.
 
thank you,
I use an extra process for clr signal ,it can be true?
Code: 
process(clr)
    begin
      if (clr_in'event and clr_in='1') then
          stop_internal<='1';--clr_out<='0';
      end if; 
  end process;
process(clk,stop_internal,reset)
    variable  col_index_i:matrix1x7_2304;variable col_index_nonzero_i:matrix1x7;
    variable i:integer range 0 to 96;
    begin 
      if reset ='1' then 
        i:=0; col_index_i:=(1,1,1,1,1,1,1);
      else
        
         if (clk 'event and clk='1' )and stop_internal='1' then
           col_index_i:=(1,1,1,1,1,1,1);
           
          if i=96 then
            clr_out<='1';
            stop_internal<='0';
            i:=1; 
          else
           clr_out<='0';
           i:=i+1;
          end if;
        
          end if;
        end if;
         
      --end if;
    end process;
 

Generates an error "multiple drivers" for signal stop_internal.
 

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