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Yes buffers are used to restore the signal, but when you use any cell, be it buffer or inverter, these cells have some delay associated with them. So when you add any cell to your path the path delay increases. Since buffer or 2 inverters are the simplest form of cells, buffers are used. For fixing hold, there are special delay buffers present in your library, they are used.
If you look at Hold time equation Tcq + Tcomb> Tskew + Thold. Hold violation occurs due to faster datapath. If we increase datapath delay. It will solve hold violation and adding buffer in datapath will increase datapath delay.
If you look at Hold time equation Tcq + Tcomb> Tskew + Thold. Hold violation occurs due to faster datapath. If we increase datapath delay. It will solve hold violation and adding buffer in datapath will increase datapath delay.
By data path delay you mean Tcomb right? but consider the setup time equation Tclk + Tskew>Tcq + Tcomb + Tsu .So an increase in Tcomb to fix hold time will essentially make the circuit operate at lesser freq( because of setup time). So is there a better way to optimize both setup and hold time considerations?
You can increase datapath delay (insert buffer) only you have enough setup margin else you will end up having setup violation. If your path is having hold violations and setup critical also, than buffer location becomes very important.
But i suppose in practice we always set a target clock frequency while designing the chip itself which means that Tclk is fixed. since Tcq and Tsu are also fixed at the synthesis stage. The only parameters that we control are Tcomb and Tskew. We would like to have high Tcomb for hold time check and high skew for higher running freq without violating setup time. But it is important to note that (Tcomb)max is limited by setup while (Tskew)max is limited by hold time. The interplay between these two has to be controlled carefully to run at the right freq( without violating setup) and ensure proper data is sampled(without violating hold).
please let me know if my understanding is right
Setup time:-The minimumm amount of time taken by the data signal that should be held steady or stable before the arrival of active edge of clock
equation:-Tcq+Tcombi<=Tcp-Tsetup
Hold time:-The minimumm amount of time taken by the data signal that should be held steady or stable after the arrival of active edge of clock
equation:-Tcq+Tcombi>=Thold
If data arrival time(Tcq+Tcombi)is greater than data required time(Tcp-Tsetup) then setup is violated....,we can fix the setup violations can be fixed by following techniques
1.cell sizing increase(launch flop)
2.combi delay decrease
3.Net length decrease
4.Clock period increase
If data arrival time(Tcq+Tcombi)is less than data required time(Tcp-Tsetup) then hold is violated....,we can fix the hold violations can be fixed by following techniques
1.Cell down sizing(lunch flop)
2.net length increase
3.combi delay increase
Buffers are generally used to correct hold violations. To correct setup violations: consider Tclk> Tcq + Tcomb + Tsu - Tskew
suppose ur Tclk is fixed:
method 1: Try to decrease your Tcomb by pipelining etc
method 2: You might want to increase Tskew (By adding buffers in the capture path. But then again make sure that the increase in Tskew does not result in a hold violation since Tskew < Tcq + Tcomb - Thold
But i would suggest you try method1 before attempting method2
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