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VHDL initialization problem

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madalin1990

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Hi!I am trying to write a elevator controller!for this elevator I have defined an inout pin called NIVEL.The problem is when i am trying to simulate this controller NIVEL is high impedance Z.I think the problem is in the following code lines:
Code: 
if CLK'event and CLK = '1' then
	if kr=0  then	
		Sreg0 <= INITIAL;
		NIVEL <= "10000";
		
	else....

Is this assigment correct?
 

Dear Madalin1990,

I have 3 questions -
Is kr an integer ?
Did you try initializing nivel ?
And whats in the ELSE section?

I think you should try rising_edge instead of clk'event , it has simulation advantage, when you specifically needs an event 0 to 1 .
 

madalin1990 said:
Hi!I am trying to write a elevator controller!for this elevator I have defined an inout pin called NIVEL.The problem is when i am trying to simulate this controller NIVEL is high impedance Z.I think the problem is in the following code lines:
Code: 
if CLK'event and CLK = '1' then
	if kr=0  then	
		Sreg0 <= INITIAL;
		NIVEL <= "10000";
		
	else....

Is this assigment correct?
Click to expand...

The problem is not in the code that you posted. Simple inspection shows that NIVEL is never set to to Z in the code that you posted, therefore the problem is elsewhere.

On the assumption that you have declared NIVEL like this...
NIVEL: inout std_logic_vector(4 downto 0) := (others > 'Z'); -- Or perhaps := "ZZZZZ"
Then NIVEL would get an initial value of all Z. Then the problem would be simply one of the following:
- CLK is not changing from 0 to 1
- kr is not equal to 0 at the rising edge of CLK

Kevin Jennings
 
Here it is the entire code of the elevator entity:
Code: 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all; 
LIBRARY WORK;
USE WORK.de_transformare.ALL;

entity lift is 
	port (
		B: in STD_LOGIC_VECTOR (0 to 4);
		CLK: in STD_LOGIC;
		R: in STD_LOGIC_VECTOR (0 to 4);
		AD: out STD_LOGIC;
		DOWN: out STD_LOGIC;
		SENS: out STD_LOGIC;
		UP: out STD_LOGIC;
		NIVEL: inout STD_LOGIC_VECTOR (0 to 4));
		
end;

architecture lift_arch of lift is

-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (INITIAL,INACTIV, ACTIVR, COBOARAR, ASTEAPTA1, ASTEAPTA2, ASTEAPTA3, ASTEAPTA4, ASTEAPTA5, ACTIVB, URCAB, COBOARAB, URCAR);
-- attribute enum_encoding of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding

signal Sreg0: Sreg0_type;


begin
-- concurrent signals assignments
-- diagram ACTION


----------------------------------------------------------------------
-- Machine: Sreg0
----------------------------------------------------------------------
Sreg0_machine: process (CLK) 

variable kn    :natural;
variable kb    :natural;		
variable kr    :natural;

begin
Sreg0 <= INITIAL;
kr:=transformare(R); 
kb:=transformare(B);
kn:=transformare(NIVEL);
if CLK'event and CLK = '1' then
	if kr=0  then	
		Sreg0 <= INITIAL;
		-- Set default values for registered outputs/signals and for variables
		-- ...	 
		NIVEL<="10000";
	else
		-- Set default values for registered outputs/signals and for variables
		-- ...
		case Sreg0 is  
			when INITIAL =>
					Sreg0 <= INACTIV;
			when INACTIV =>
				if kr>0  then	
					Sreg0 <= ACTIVR;
				elsif kr=0 then	
					Sreg0 <= INACTIV;
				end if;
			when ACTIVR =>
				if kn>kr then 	
					Sreg0 <= COBOARAR;
				elsif kn=kr then	
					Sreg0 <= ASTEAPTA1;
				elsif kn<kr then	
					Sreg0 <= URCAR;
				end if;
			when COBOARAR =>
				if kn=kr then	
					Sreg0 <= ASTEAPTA1;
				elsif kn>kr and CLK'event and CLK = '1' then	
					Sreg0 <= COBOARAR;
					kn:=transformare(NIVEL);
				end if;
			when ASTEAPTA1 =>
				if kb>0 then	
					Sreg0 <= ACTIVB;
				elsif kb=0 and CLK'event and CLK = '1' then	
					Sreg0 <= ASTEAPTA2;
				end if;
			when ASTEAPTA2 =>
				if kb>0 then	
					Sreg0 <= ACTIVB;
				elsif kb=0 and CLK'event and CLK = '1' then	
					Sreg0 <= ASTEAPTA3;
				end if;
			when ASTEAPTA3 =>
				if kb>0 then	
					Sreg0 <= ACTIVB;
				elsif kb=0 and CLK'event and CLK = '1' then	
					Sreg0 <= ASTEAPTA4;
				end if;
			when ASTEAPTA4 =>
				if kb>0 then	
					Sreg0 <= ACTIVB;
				elsif kb=0 and CLK'event and CLK = '1' then	
					Sreg0 <= ASTEAPTA5;
				end if;
			when ASTEAPTA5 =>
				if kb>0 then	
					Sreg0 <= ACTIVB;  
				elsif kb=0 and CLK'event and CLK = '1' then	
					Sreg0 <= INACTIV;	
				end if;
			when ACTIVB =>
				if kn>kb then	
					Sreg0 <= COBOARAB; 
				elsif kn<kb then	
					Sreg0 <= URCAB;	
				elsif kn=kb then	
					Sreg0 <= ASTEAPTA1;
				end if;
			when URCAB =>
				if kn=kb then	
					Sreg0 <= ASTEAPTA1;
				elsif kn<kb and CLK'event and CLK = '1' then	
					Sreg0 <= URCAB;	 
					kn:=transformare(NIVEL);
				end if;
			when COBOARAB =>
				if kn=kb then	
					Sreg0 <= ASTEAPTA1;
				elsif kn>kb and CLK'event and CLK = '1' then	
					Sreg0 <= COBOARAB; 
					kn:=transformare(NIVEL);
				end if;
			when URCAR =>
				if kn=kr then	
					Sreg0 <= ASTEAPTA1;
				elsif kn<kr and CLK'event and CLK = '1' then	
					Sreg0 <= URCAR;
					kn:=transformare(NIVEL);
				end if;
			when others =>
				null;
		end case;
	end if;
end if;
end process;

-- signal assignment statements for combinatorial outputs
AD_assignment:
AD <= '0' when (Sreg0 = INACTIV) else
      '1' when (Sreg0 = ACTIVR) else
      '0';

UP_assignment:
UP <= '0' when (Sreg0 = INACTIV) else
      '0' when (Sreg0 = COBOARAR) else
      '0' when (Sreg0 = ASTEAPTA1) else
      '0' when (Sreg0 = ASTEAPTA2) else
      '0' when (Sreg0 = ASTEAPTA3) else
      '0' when (Sreg0 = ASTEAPTA4) else
      '0' when (Sreg0 = ASTEAPTA5) else
      '1' when (Sreg0 = URCAB) else
      '0' when (Sreg0 = COBOARAB) else
      '1' when (Sreg0 = URCAR) else
      '0';

DOWN_assignment:
DOWN <= '0' when (Sreg0 = INACTIV) else
        '1' when (Sreg0 = COBOARAR) else
        '0' when (Sreg0 = ASTEAPTA1) else
        '0' when (Sreg0 = ASTEAPTA2) else
        '0' when (Sreg0 = ASTEAPTA3) else
        '0' when (Sreg0 = ASTEAPTA4) else
        '0' when (Sreg0 = ASTEAPTA5) else
        '0' when (Sreg0 = URCAB) else
        '1' when (Sreg0 = COBOARAB) else
        '0' when (Sreg0 = URCAR) else
        '0';

SENS_assignment:
SENS <= '0' when (Sreg0 = COBOARAR) else
        '1' when (Sreg0 = URCAB) else
        '0' when (Sreg0 = COBOARAB) else
        '1' when (Sreg0 = URCAR) else
        '1';

NIVEL_0_assignment:
NIVEL(0) <= NIVEL(1) when (Sreg0 = COBOARAR) else
            '0' when (Sreg0 = URCAB) else
            NIVEL(1) when (Sreg0 = COBOARAB) else
            '0' when (Sreg0 = URCAR) else
            '0';

NIVEL_1_assignment:
NIVEL(1) <= NIVEL(2) when (Sreg0 = COBOARAR) else
            NIVEL(0) when (Sreg0 = URCAB) else
            NIVEL(2) when (Sreg0 = COBOARAB) else
            NIVEL(0) when (Sreg0 = URCAR) else
            NIVEL(0);

NIVEL_2_assignment:
NIVEL(2) <= NIVEL(3) when (Sreg0 = COBOARAR) else
            NIVEL(1) when (Sreg0 = URCAB) else
            NIVEL(3) when (Sreg0 = COBOARAB) else
            NIVEL(1) when (Sreg0 = URCAR) else
            NIVEL(1);

NIVEL_3_assignment:
NIVEL(3) <= NIVEL(4) when (Sreg0 = COBOARAR) else
            NIVEL(2) when (Sreg0 = URCAB) else
            NIVEL(4) when (Sreg0 = COBOARAB) else
            NIVEL(2) when (Sreg0 = URCAR) else
            NIVEL(2);

NIVEL_4_assignment:
NIVEL(4) <= '0' when (Sreg0 = COBOARAR) else
            NIVEL(3) when (Sreg0 = URCAB) else
            '0' when (Sreg0 = COBOARAB) else
            NIVEL(3) when (Sreg0 = URCAR) else
            NIVEL(3);

end lift_arch;

The function "transformare" is a request resolver!
The problem i encounter now is that although i have initialized NIVEL="10000" when i simulate NIVEL takes the value XXXXX.
Stranger is that when NIVEL="00001" when i simulate NIVEL takes the value 0000X.
 
Last edited:

Its because you're driving NIVEL from the process and outside the process. You can only assign it in one or the other, not both. This is causing the 'X' values.
 

And how can i modify the code to correct this error and make the program work?
 

either remove the NIVEL assignment from the process or remove the NIVEL assignment that is outside the process.
 
I have passed this error tnx to your advice!Thank you!
But now i have a new problem:
In the testbench I have assigned this signals:
Code: 
Br<="00000" ;
Rr<="00000"	, "00010" after 5000 ns;
Stim_CLKr:process
begin
  CLKr <='0'; wait for 500 ns;
	CLKr <='1'; wait for 500 ns;

Although NIVEL should pass from 10000 to 01000 to 00100 to 00010 ,it passes from 10000 to 00000 and remains there.
I will attach the elevator entity description with the new updates:
Code: 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all; 
LIBRARY WORK;
USE WORK.de_transformare.ALL;

entity lift is 
	port (
		B: in STD_LOGIC_VECTOR (0 to 4);
		CLK: in STD_LOGIC;
		R: in STD_LOGIC_VECTOR (0 to 4);
		AD: out STD_LOGIC;
		DOWN: out STD_LOGIC;
		SENS: out STD_LOGIC;
		UP: out STD_LOGIC;
		NIVEL: inout STD_LOGIC_VECTOR (0 to 4));
end;

architecture lift_arch of lift is

-- SYMBOLIC ENCODED state machine: Sreg0
type Sreg0_type is (INITIAL,INACTIV, ACTIVR, COBOARAR, ASTEAPTA1, ASTEAPTA2, ASTEAPTA3, ASTEAPTA4, ASTEAPTA5, ACTIVB, URCAB, COBOARAB, URCAR);
-- attribute enum_encoding of Sreg0_type: type is ... -- enum_encoding attribute is not supported for symbolic encoding

signal Sreg0: Sreg0_type;


begin
-- concurrent signals assignments
-- diagram ACTION


----------------------------------------------------------------------
-- Machine: Sreg0
----------------------------------------------------------------------
Sreg0_machine: process (CLK) 

variable kn    :natural;
variable kb    :natural;		
variable kr    :natural;

begin
kr:=transformare(R); 
kb:=transformare(B);
kn:=transformare(NIVEL);
if CLK'event and CLK = '1' then
	if kr=0  then	
		Sreg0 <= INITIAL;
			 
		
	else
		-- Set default values for registered outputs/signals and for variables
		-- ...
		case Sreg0 is  
			when INITIAL =>
					Sreg0 <= INACTIV;
			when INACTIV =>
				if kr>0  then	
					Sreg0 <= ACTIVR;
				elsif kr=0 then	
					Sreg0 <= INACTIV;
				end if;
			when ACTIVR =>
				if kn>kr then 	
					Sreg0 <= COBOARAR;
				elsif kn=kr then	
					Sreg0 <= ASTEAPTA1;
				elsif kn<kr then	
					Sreg0 <= URCAR;
				end if;
			when COBOARAR =>
				if kn=kr then	
					Sreg0 <= ASTEAPTA1;
				elsif kn>kr and CLK'event and CLK = '1' then	
					Sreg0 <= COBOARAR;
					kn:=transformare(NIVEL);
				end if;
			when ASTEAPTA1 =>
				if kb>0 then	
					Sreg0 <= ACTIVB;
				elsif kb=0 and CLK'event and CLK = '1' then	
					Sreg0 <= ASTEAPTA2;
				end if;
			when ASTEAPTA2 =>
				if kb>0 then	
					Sreg0 <= ACTIVB;
				elsif kb=0 and CLK'event and CLK = '1' then	
					Sreg0 <= ASTEAPTA3;
				end if;
			when ASTEAPTA3 =>
				if kb>0 then	
					Sreg0 <= ACTIVB;
				elsif kb=0 and CLK'event and CLK = '1' then	
					Sreg0 <= ASTEAPTA4;
				end if;
			when ASTEAPTA4 =>
				if kb>0 then	
					Sreg0 <= ACTIVB;
				elsif kb=0 and CLK'event and CLK = '1' then	
					Sreg0 <= ASTEAPTA5;
				end if;
			when ASTEAPTA5 =>
				if kb>0 then	
					Sreg0 <= ACTIVB;  
				elsif kb=0 and CLK'event and CLK = '1' then	
					Sreg0 <= INACTIV;	
				end if;
			when ACTIVB =>
				if kn>kb then	
					Sreg0 <= COBOARAB; 
				elsif kn<kb then	
					Sreg0 <= URCAB;	
				elsif kn=kb then	
					Sreg0 <= ASTEAPTA1;
				end if;
			when URCAB =>
				if kn=kb then	
					Sreg0 <= ASTEAPTA1;
				elsif kn<kb and CLK'event and CLK = '1' then	
					Sreg0 <= URCAB;	 
					kn:=transformare(NIVEL);
				end if;
			when COBOARAB =>
				if kn=kb then	
					Sreg0 <= ASTEAPTA1;
				elsif kn>kb and CLK'event and CLK = '1' then	
					Sreg0 <= COBOARAB; 
					kn:=transformare(NIVEL);
				end if;
			when URCAR =>
				if kn=kr then	
					Sreg0 <= ASTEAPTA1;
				elsif kn<kr and CLK'event and CLK = '1' then	
					Sreg0 <= URCAR;
					kn:=transformare(NIVEL);
				end if;
			when others =>
				null;
		end case;
	end if;
end if;           
end process;


-- signal assignment statements for combinatorial outputs
AD_assignment:
AD <= '0' when (Sreg0 = INACTIV) else
      '1' when (Sreg0 = ACTIVR) else
      '0';

UP_assignment:
UP <= '0' when (Sreg0 = INACTIV) else
      '0' when (Sreg0 = COBOARAR) else
      '0' when (Sreg0 = ASTEAPTA1) else
      '0' when (Sreg0 = ASTEAPTA2) else
      '0' when (Sreg0 = ASTEAPTA3) else
      '0' when (Sreg0 = ASTEAPTA4) else
      '0' when (Sreg0 = ASTEAPTA5) else
      '1' when (Sreg0 = URCAB) else
      '0' when (Sreg0 = COBOARAB) else
      '1' when (Sreg0 = URCAR) else
      '0';

DOWN_assignment:
DOWN <= '0' when (Sreg0 = INACTIV) else
        '1' when (Sreg0 = COBOARAR) else
        '0' when (Sreg0 = ASTEAPTA1) else
        '0' when (Sreg0 = ASTEAPTA2) else
        '0' when (Sreg0 = ASTEAPTA3) else
        '0' when (Sreg0 = ASTEAPTA4) else
        '0' when (Sreg0 = ASTEAPTA5) else
        '0' when (Sreg0 = URCAB) else
        '1' when (Sreg0 = COBOARAB) else
        '0' when (Sreg0 = URCAR) else
        '0';

SENS_assignment:
SENS <= '0' when (Sreg0 = COBOARAR) else
        '1' when (Sreg0 = URCAB) else
        '0' when (Sreg0 = COBOARAB) else
        '1' when (Sreg0 = URCAR) else
        '1';


NIVEL_0_assignment:
NIVEL(0) <= NIVEL(1) when (Sreg0 = COBOARAR) else
            '0' when (Sreg0 = URCAB) else
            NIVEL(1) when (Sreg0 = COBOARAB) else
            '0' when (Sreg0 = URCAR) else
            '1' when (Sreg0 = INITIAL);
            

NIVEL_1_assignment:
NIVEL(1) <= NIVEL(2) when (Sreg0 = COBOARAR) else
            NIVEL(0) when (Sreg0 = URCAB) else
            NIVEL(2) when (Sreg0 = COBOARAB) else
            NIVEL(0) when (Sreg0 = URCAR) else
            '0' when (Sreg0 = INITIAL);

NIVEL_2_assignment:
NIVEL(2) <= NIVEL(3) when (Sreg0 = COBOARAR) else
            NIVEL(1) when (Sreg0 = URCAB) else
            NIVEL(3) when (Sreg0 = COBOARAB) else
            NIVEL(1) when (Sreg0 = URCAR) else
            '0' when (Sreg0 = INITIAL) ;
            
NIVEL_3_assignment:
NIVEL(3) <= NIVEL(4) when (Sreg0 = COBOARAR) else
            NIVEL(2) when (Sreg0 = URCAB) else
            NIVEL(4) when (Sreg0 = COBOARAB) else
            NIVEL(2) when (Sreg0 = URCAR) else
            '0' when (Sreg0 = INITIAL) ;

NIVEL_4_assignment:
NIVEL(4) <= '0' when (Sreg0 = COBOARAR) else
            NIVEL(3) when (Sreg0 = URCAB) else
            '0' when (Sreg0 = COBOARAB) else
            NIVEL(3) when (Sreg0 = URCAR) else
            '0' when (Sreg0 = INITIAL) ;
            
end lift_arch;
 

I just can't find the error.I think the error is in this code but i can't find it:
Code: 
NIVEL_0_assignment:
NIVEL(0) <= NIVEL(1) when (State = DOWNR) else
            '0' when (State = UPB) else
            NIVEL(1) when (State = DOWNB) else
            '0' when (State = UPR) else
            '1' when (State = INITIAL) else
            NIVEL(0) when (State=INACTIV) else
            NIVEL(0) when (State=ACTIVR)
          else 'X';
            

NIVEL_1_assignment:
NIVEL(1) <= NIVEL(2) when (State = DOWNR) else
            NIVEL(0) when (State = UPB) else
            NIVEL(2) when (State = DOWNB) else
            NIVEL(0) when (State= UPR) else
            '0' when (State = INITIAL) else
            NIVEL(1) when (State=INACTIV) else
            NIVEL(1) when (State=ACTIVR)
          else 'X'; 
NIVEL_2_assignment:
NIVEL(2) <= NIVEL(3) when (State = DOWNR) else
            NIVEL(1) when (State = UPB) else
            NIVEL(3) when (State = DOWNB) else
            NIVEL(1) when (State = UPR) else
            '0' when (State = INITIAL) else
            NIVEL(2) when (State=INACTIV) else 
            NIVEL(2) when (State=ACTIVR)
          else 'X';
            
NIVEL_3_assignment:
NIVEL(3) <= NIVEL(4) when (State = DOWNR) else
            NIVEL(2) when (State = UPB) else
            NIVEL(4) when (State = DOWNB) else
            NIVEL(2) when (State = UPR) else
            '0' when (State = INITIAL) else
            NIVEL(3) when (State=INACTIV) else
            NIVEL(3) when (State=ACTIVR)
          else 'X';

NIVEL_4_assignment:
NIVEL(4) <= '0' when (State = DOWNR) else
            NIVEL(3) when (State = UPB) else
            '0' when (State = DOWNB) else
            NIVEL(3) when (State = UPR) else
            '0' when (State = INITIAL) else
            NIVEL(4) when (State=INACTIV) else
            NIVEL(4) when (State=ACTIVR)
          else 'X';
 

well, you'll have to monitor the state signal to see if it is changing as you expected. And then make sure your assignments are correct.
WIthout specific questions, we cant help, and we're not here to do your work for you.

Its not working, can you fix it, is not a good question.
 

TrickyDicky said:
well, you'll have to monitor the state signal to see if it is changing as you expected. And then make sure your assignments are correct.
WIthout specific questions, we cant help, and we're not here to do your work for you.

Its not working, can you fix it, is not a good question.
Click to expand...

Sorry.It's because I am out of time!
Question:If I write NIVEL(0),NIVEL(1),NIVEL(2) and I assign them using non-blocking assigment,it will affect the assigment if NIVEL is declared "0 to 2" or "2 downto 0".I mean NIVEL(0) will assign to the least significant bit in both cases?
 

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