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why do we need to avoid combinational logic in the code for fpga?

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VLSI_CHE

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can anyone explain ingeneral and in terms of internal fpga placement and routing?
 

Can you explain in your own words what combinational logic is, and how it is different from any other type of logic you can think of? That should get you in the right direction of an answer.
 

Well to my understanding,

1- Combination logic is better to avoid in cases because it will cause the delay between the sequential components to increase, if place between the sequential components, hence reducing the optimum frequency for the design
2- Combinational feedback loop are difficult to tackle with than sequential feedback, hence wherever possible avoid combination feedback loop(coz of issues like race etc.)

But it is only when you can choose between selecting sequential and combinational logic, not always...Of course things vary case to case....: )
 

Come on, You cannot avoid Combinational logic!!!.
Without combinational logics, there is no single device on earth could work.....I think you did not understand it fully. Combo logics are always there...It is the user how to properly route it.
 

We often try to design "synchronous" design and try to bound combinatorial logic with flops for better timing, if that's what you meant.
 

yes, this is what meant. what happens in the routing if we do not bound the combnational logic with flops?
 

In synchronous design, what's important is the propagation delay from one flop to the next flop through combinatorial logics and routes. That is because it determines how fast the circuit can run.
For example, if we have a design and if there is a long combinatorial path between two flops, that path will be the critical path of the design. In other words, that will limit the max clock frequency the design can run.
Breaking a combinatorial design and inserting flops in between is called pipelining. You can find more reference on it by searching online.
 

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yes, this is what meant. what happens in the routing if we do not bound the combnational logic with flops?

Your design will most probably fail in case if your timing budget is so tight.
 

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