rf, microwave simulation vs measurement

Hi all

As a designer, you may once or twice face the case that your design measurement's performances are significantly different from simulation's. For examples gain is much degraded.
Normally, everything is done in the simulation: layout optimization, extraction simulation ...

So I just wonder where does the discrepancy come from?
- Due to device models? (Provided by the commercial foundries)
- Due to simulator?
...

If you have ever had any ideas regarding this, please advise. Any discussion is appreciated.

Thank you all.

Simulation and the real world rarely coincide.
in simulation everything is ideal it doesnt really take into account component tolerances

the circuit, once built with real components with their widely varying tolerances
transistors and other semiconductors that the gain is a little more or less than the simulation example
wire wound and stripline inductor variations

there are just so, so many variables to contend with

cheers
Dave

Thank you Dave. I totally agree with what you said. The thing is, assuming we go through all the optimization, all kind of simulations available then we get the target simulation results. However when we get the chip back to measure, still there is big gap between measurement results and simulation results. What can we do at this point?

What is the circuit/device? Frequency range? What type of simulation have you used? Which parameters do not agree?

Hi Volker
I design LNA at 60 GHz. I used SP analysis of SpectreRF. The design has been RC extracted using Assura QRC. Simulation shows 27 dB S21 while measurement is 10 dB. The LNA was measured using probe station, so the measurement environment can be considered almost the same as simulation environment.

rfle said:

Simulation shows 27 dB S21 while measurement is 10 dB.

Click to expand...

That's a substantial difference indeed ...

At this frequency, layout effects (including inductance!) are relevant and it makes sense to use fullwave EM simulation. I've been supporting the EM modelling for different groups doing mm-wave designs, e.g. 77 GHz radar frontend. These customers have very nice agreement between simulated and measured. Components which are EM simulated using Sonnet in these designs: inductors, transformers and some interconnects.

About EM modeling, I do not know why you have to make the model for inductor and transformer, does the PDK not provide those? And are you able to do EM modeling for the active component also?

Assura QRC extraction is not very robust extraction utility at those frequencies.It neglects inductors and mutual couplings between the lines.
Therefore EM simulation necessary..
In additional to this, model discrepencies,packaging effects,unpredictible manufacturing tolerances are also effective.

rfle said:

About EM modeling, I do not know why you have to make the model for inductor and transformer, does the PDK not provide those?

Click to expand...

It depends on the technology, frequency and the inductor/transformer value and topology needed. If your PDK has the values that you need, and models are validated at your operating frequency, you can use them.

rfle said:

And are you able to do EM modeling for the active component also?

Click to expand...

EM is usually about the passive (layout) part, to get the passive components right and accurately model the interconnects.
At 24GHz and above, I see some users model the transistor layout parasitics, i.e. vias and metals inside the transistor (but excluding the actual nonlinear device).

I don't know if your problem is the lack of EM modelling, or something trivial. Your error is so very large that it might be some trivial mistake.

BigBoss said:

Assura QRC extraction is not very robust extraction utility at those frequencies.It neglects inductors and mutual couplings between the lines.
Therefore EM simulation necessary..
In additional to this, model discrepencies,packaging effects,unpredictible manufacturing tolerances are also effective.

Click to expand...

That makes sense, thank you.

EM is usually about the passive (layout) part, to get the passive components right and accurately model the interconnects

Click to expand...

Confirmed, thanks

Now the causes for my chip'performance degradation seems clearer. I only use Assura QRC for the extraction, as BigBoss said, it is not robust at 60GHz. Thank you all.