Voltage filtering for fpga from ldo or switcher

Hello.

I am designing fpga board and i have one power source that need to supply same voltage levels to different fpga pins and i need some sort of filter to separate between them could u suggest me some?
Thx.

use a LC filter... close to LDO
use decoupling caps near the pins as per the fpga vendor suggestion...

Thx,u meant lc filter on the intersection were the Vout from ldo splits to 2 diffrenet pins?

The split to pins of fpga must be after the LC filter.

Using LC is one solution. The reason for using LC filter it eliminates high frequency noise. You might know the formula of cut off frequency for the same...1/2*pi*root(L*C)
You have to select the values of L and C after making basic study of noise you are expecting from your supply.

Also, you can do with only decoupling caps without L. The only problem is you have to use high value of capacitor as the trace inductance is very very less.

In case of quick current transitions from regulator, i.e., if your load current varies quickly, the inductor may not be able to respond that quickly. We all know that inductor doesn't allow sudden transition in current.

Considering these all criteria, better go for capacitor solution rather than using inductor.

Hello.
Thx u r helpping me can u please explain me what u meant when that i need to use high value of capacitor because "trace inductance is very very less."

Did u meant that the cap i will place will be toghter with a strip as a LP filter?

Thx.

There are a few cases where separate supply filtering of FPGA pins can be reasonable, e.g. analog PLL supply pins. The succepcibility to supply noise depends on chip design details, thus I doubt that a general discussion without referring to a particular vendor and FPGA family makes much sense. The first source of information should be vendor reference manuals and application notes.

A state-of-the-art digital PCB will have power supply planes and a larger number of distributed bypass capacitors for each supply node. Splitting supply nets at the voltage regulator seems inappropriate in this situation. You all rather place local filters for sensitive supply pins, e.g. ferrite bead/capacitor combinations or RC filters for supply pins with low to moderate current consumption. LC filters without sufficient dampening involves a risk of oscillations brought up by current transients, their usability should be checked thoroughly.

Thx u r helpping me can u please explain me what u meant when that i need to use high value of capacitor because "trace inductance is very very less."

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I was talking if you use only decoupling caps instead of LC... In the case where you use only caps, the LC effect is the combination of trace impedance+decoupling caps, for a normal trace inductance is very less, so, to get the same LC effect you use higher value of caps...

These are all general considerations.. As FvM was mentioning finally you must have a look at your vendor suggestions...

A state-of-the-art digital PCB will have power supply planes and a larger number of distributed bypass capacitors for each supply node. Splitting supply nets at the voltage regulator seems inappropriate in this situation.

Click to expand...

@iliya24
This is very important... what is your board layer count?

LC filters without sufficient dampening involves a risk of oscillations brought up by current transients, their usability should be checked thoroughly.

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As FvM was mentioning, regulators have feedback mechanism and it must be stable,...

Thx, i layer count is 8.

Could u send me a link that i can learn about lc dumping...
Thank you