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Error in IC compiler while implementing MUX program

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priyanka24

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Hi...

i have implemented my MUX program and trying to implement in through vcs, dc compiler, ic compiler.

but me getting following error in IC compiler:

 

Re: error in IC compiler

From the error message shown by the IC compiler, it seems that your core utilization is over 100% and thus IC compiler can't continue the placement. Maybe you can solve this by lower utilization rate when "specify the floorplan" or "initialize the floorplan."
 
Re: error in IC compiler

YuLongHuang said:
From the error message shown by the IC compiler, it seems that your core utilization is over 100% and thus IC compiler can't continue the placement. Maybe you can solve this by lower utilization rate when "specify the floorplan" or "initialize the floorplan."
Click to expand...

i have kept my core utilization as 0.7
 

Re: error in IC compiler

Could you talk about your design functionality ?
It helps us with the estimation of scale/property of the design.
For example, the design is too small such that room for improvement with 0.3*area is also small.
 

Re: error in IC compiler

YuLongHuang said:
Could you talk about your design functionality ?
It helps us with the estimation of scale/property of the design.
For example, the design is too small such that room for improvement with 0.3*area is also small.
Click to expand...

this is simple MUX design. to understand flow me first trying MUX.
 

Re: error in IC compiler

I guess so. 4-to-1 MUX is so small that it's just composed of several gates.
The room for adding more optimization device is 0.3*(cell area) which is also small.

Could you tell me which the stage is when the error occurs ? floorplanning ? powerplanning ? placement ? CTS ? routing ? manufacturing ?
To be more specifically, it's clues that we have to know which devices may be added.
Once the optimized device is supposed to add into the design, the remaining room is seemed to be insufficient.
 

Re: error in IC compiler

YuLongHuang said:
I guess so. 4-to-1 MUX is so small that it's just composed of several gates.
The room for adding more optimization device is 0.3*(cell area) which is also small.

Could you tell me which the stage is when the error occurs ? floorplanning ? powerplanning ? placement ? CTS ? routing ? manufacturing ?
To be more specifically, it's clues that we have to know which devices may be added.
Once the optimized device is supposed to add into the design, the remaining room is seemed to be insufficient.
Click to expand...

error coming after core placement and optimization.
 

Re: error in IC compiler

Actually, I have no idea which device maybe added since your design is so small.
For example, buffer is added for fixing hold time or high fan-out. But in your case, it seem irrelevant.

There is another debug view for your case. You can open the layout view and zoom in the design.
The layout will show the placed/unplaced std cell and you can check out why the cell can't be placed.
 

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