Writing synthesizable task in verilog

Can we use tasks (or functions) in sequential always blocks in synthesizable verilog code??

I couldnt find any proper set of guidelines or rules describing the use of tasks and functions for synthesis.

I know we are not supposed to use timing control statements such as @, wait, #delay, etc in tasks, and we must use blocking assignments, and use tasks to describe combinatorial logic only and not sequential.

But what happens if we declare this combinatorial task/function, and then use it inside a clocked always block.
e.g. I want to make a pipelined adder with 2 stages which adds a & b in first stage, then adds c to the result in stage 2. Here's the code



Is this a synthesizable code??

I wrote a similar design, but quite complex, which is not giving any synthesis errors/warnings. But I dont know if it would produce any simulation mismatches??

I tried searching for a straightforward answer regarding synthesis of tasks/functions but nowhere found a clear description. Some texts say that we can use the outputs of tasks in synchronous always blocks thats all i found.

Perhaps this could help you: **broken link removed**

Yes, you can use tasks inside a clocked always block and your code is synthesizable. You can (and should) use tasks to replicate repetitive code without adding a lot of code lines. I do it all the time and it works without a problem. Just a note: you don't have to use only blocking assignments inside tasks, you can use non-blocking too.

But if I use blocking assignment inside a task and use that task in a sequential block (as in the example above), wouldnt it be inappropriate i.e. indirectly mixing blocking and non-blocking assignments.

Not really, you can do whatever you want. As a rule I use only non-blocking for synthesizable code but there is nothing wrong with using both types of assignments, as long as you know what you're doing.

fcfusion said:

Not really, you can do whatever you want. As a rule I use only non-blocking for synthesizable code but there is nothing wrong with using both types of assignments, as long as you know what you're doing.

Click to expand...

Unfortunately, most people do not know what they are doing, or don't know enough about what they are doing.

Two rules to live by that I know of no exceptions:

1. Always use blocking assignments for combinatorial or level-sensitive code, as well a clock assignments
2. Always use non-blocking assignments for variables that are written on a clock edge, and read on the same clock edge in another process.

dave_59 said:

Unfortunately, most people do not know what they are doing, or don't know enough about what they are doing.

Two rules to live by that I know of no exceptions:

1. Always use blocking assignments for combinatorial or level-sensitive code, as well a clock assignments
2. Always use non-blocking assignments for variables that are written on a clock edge, and read on the same clock edge in another process.

Click to expand...

Exactly... these are the rules that I follow for writing synthesizable code. And thats why I am confused about using tasks containing blocking assignments in sequential blocks. Doesn't this mix up blocking and non blocking assignments violating the above mentioned rules.

Or, with the use of tasks are we defining the combinational logic separately that is supposed to be in between two sequential elements (e.g. piplines with combinational logic)??

Does instantiating the task inside sequential block mean that we are only providing inputs to the combinatorial task from sequential elements and taking outputs from it, while the combinational logic itself inside the task is completely independent of the clock edges and is still combinatorial??

Thanks
Siddhartha

https://www.asic-world.com/verilog/synthesis2.html#Example_of_Non-Synthesizable_Verilog_construct.

Hope this wud b useful for yr question regarding taks and functions