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VHDL generic flip flop cascading

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shaiko

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Please help me describe the following t flip flop cascade in a generic fashsion :

Code:
	process ( clk_i , rst_i ) is 
	begin
		if RST_I = '1' then 
			temp1 <= '0' ;
			temp2 <= '0' ;
			temp3 <= '0' ;
			temp4 <= '0' ;
			temp5 <= '0' ;
			temp6 <= '0' ;		
		elsif rising_edge (	clk_i ) then
			temp1 <= not temp1 ;
			if temp1 = '1' then 
				temp2 <= not temp2 ;
				if temp2 = '1' then 
					temp3 <= not temp3 ;
					if temp3 = '1' then 
						temp4 <= not temp4 ;
						if temp4 = '1' then 
							temp5 <= not temp5 ;
							if temp5 = '1' then 
								temp6 <= not temp6 ;	
							end if;
						end if;
					end if;
				end if;
			end if ;		
		end if; 	
	end process;
 

It is a synchronous counter. temp1 is lowest bit and temp6 is the highest.
If you have the bits in a vector of type "unsigned", you get the same effect with "temp <= temp + 1;"
 
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