boyzzun
Junior Member level 1
hi guys,i have learned abuot VHDL on modelsim and i have o problem when i learn adder 4 bit
full_adder
well i don'nt know error from adder4bit,can you help me
PHP:
--------------4-bit adder-----------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;
-----------------------------------
entity adder4 is
port ( A : in std_logic;
B : in std_logic;
CI : in std_logic;
SUM : out std_logic;
CO : out std_logic
);
end adder4;
---------------------------------------
architecture structure of adder4 is
signal C : std_logic_vector(2 downto 0);
component full_adder
port (
A : in std_logic;
B : in std_logic;
Cin : in std_logic;
S : out std_logic;
Cout : out std_logic
);
end component;
for u0: full_adder use entity work.full_adder(dataflow);
for u1: full_adder use entity work.full_adder(dataflow);
for u2: full_adder use entity work.full_adder(dataflow);
for u3: full_adder use entity work.full_adder(dataflow);
begin
u0: component full_adder
port map ( A => A(0), B => B(0), Cin => CI,
S =>Sum(0), Cout => C(0));
u1 : component full_adder
port map ( A => A(1), B => B(1), Cin => C(0),
S =>Sum(1), Cout => C(1));
u2 : component full_adder
port map ( A => A(2), B => B(2), Cin => C(1),
S =>Sum(2), Cout => C(2));
u3 : component full_adder
port map ( A => A(3), B => B(3), Cin => C(2),
S =>Sum(3), Cout => CO);
end structure ;
--------------------------------------------------------------------------
PHP:
-----------full_adder---------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.ALL;
use ieee.std_logic_unsigned.ALL;
-----------------------------------
entity full_adder is
port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
S : out std_logic;
Cout : out std_logic
);
end full_adder;
--------- -----------------------------
architecture dataflow of full_adder is
begin
S <= A xor B xor Cin ;
Cout <= (A and B ) or (Cin and (A or B));
end dataflow;