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Possibly not. Generate is only to make multiple instances\copies at the time of Synthesize only based on your generic declaration. Inside a process how do you expect the generate statement to work?.
It is applicable to if generate\for generate.
---------- Post added at 13:56 ---------- Previous post was at 13:55 ----------
No you cannot. Generate is meant for conditionally creating/repeatadly creating some logic. You can however use generics inside a process - they are treated as constants, so remember the logic you may generate by using a for loop.
No you cannot. Generate is meant for conditionally creating/repeatadly creating some logic. You can however use generics inside a process - they are treated as constants, so remember the logic you may generate by using a for loop.
generate is not the end of the story. There are several generate constructs:
label : if x generate
label : for x in a to b generate
and in VHDL 2008
label : if/elsif/else x generate
label : case x generate
(a label is compulsary for generates). You cannot "exit" from a generate loop, or wait, because it is elaborated before any simulation is run.
Now, moving on to another construct, the loop:
loop --loop until wait or exit is hit
for x in a to b loop --loop from a to b, or an exit or wait is hit
while a loop --loop until a is false, or exit or wait is hit
A normal loop is just a procedural statement like most other VHDL, so has to go inside a process, function or procedure.
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