error while using pre compiled components in new architecture

i've built two components and ensured that they are doing their functionality well..
now i'm trying to connect these two components together in a new vhdl file..
i ensured that the ports are well set..

for the parent entity there is nothing to do except combining childentity1 with childentity2 through an en o/p port from childentity1 to be an i/p port for childentity2 i did this through defining en_sig in the parent architecture

i got this error message for every i/p port of childentity1 ( Formal port "clk" has OPEN or no actual associated with it.)
where clk is on of its i/p port

any idea how to overcome this..

vivo_m said:

i got this error message for every i/p port of childentity1 ( Formal port "clk" has OPEN or no actual associated with it.)
where clk is on of its i/p port

any idea how to overcome this..

Click to expand...

Is the error message not clear? You have not connected a signal to the port 'clk'. Connect it.

Kevin Jennings

this is how i connect the ports of childentity1

pb : pbup
GENERIC MAP (N => 8);
PORT MAP(clk => clk_all,
rst => rst_all,
x => x_all, --i/p
fit => fit_all, --i/p
bfit => bfit_all, --i/p
new_bfit => new_bfit_all, --o/p
en => en_sig --o/p
);

where "en" is o/p port of childentity1 and "en_sig" is signal defined in the parent architecture
those written right to "=>" are of the same port name defined in the parent entity except for en_sig
and those at its left are of the same port name defined in thechildentity1 entity

vivo_m said:

this is how i connect the ports of childentity1

pb : pbup
GENERIC MAP (N => 8);
PORT MAP(clk => clk_all,
rst => rst_all,
x => x_all, --i/p
fit => fit_all, --i/p
bfit => bfit_all, --i/p
new_bfit => new_bfit_all, --o/p
en => en_sig --o/p
);

where "en" is o/p port of childentity1 and "en_sig" is signal defined in the parent architecture
those written right to "=>" are of the same port name defined in the parent entity except for en_sig
and those at its left are of the same port name defined in thechildentity1 entity

Click to expand...

What you've shown is correct, so the next steps for somebody to help you would be:
- Post the entity and architecture code for the parent that instantiates pbup as well as at least the entity for pbup.
- What tool are you using? What version?

That will allow someone to either reproduce the problem or refute it. What you've shown you're doing looks correct, which means the problem lies in something that you haven't shown yet.

Kevin Jennings

thanks kevin

here is the full code

--Parent entity
entity p_pgbup is
generic (N : integer := 8 );
port(clk_all , rst_all : in std_logic ;
x_all : in std_logic_vector (N-1 downto 0);
fit_all : in std_logic_vector (N-1 downto 0);
bfit_all : in std_logic_vector (N-1 downto 0);
bg_all : in std_logic_vector (N-1 downto 0);
new_bfit_all : out std_logic_vector (N-1 downto 0);
new_bg_all : out std_logic_vector (N-1 downto 0)
);
end entity p_pgbup;

architecture behavioral of p_pgbup is
signal en_sig : std_logic;

--childentity1
component pbup
generic (N : integer := 8 );
port(clk , rst : in std_logic ;
x : in std_logic_vector (N-1 downto 0);
fit : in std_logic_vector (N-1 downto 0);
bfit : in std_logic_vector (N-1 downto 0);
new_bfit : out std_logic_vector (N-1 downto 0);
en : out std_logic
);
end component;

--childentity2
component pgbup
generic (N : integer := 8 );
port(clk , rst, en : in std_logic ;
x : in std_logic_vector (N-1 downto 0);
bg : in std_logic_vector (N-1 downto 0);
new_bg : out std_logic_vector (N-1 downto 0)
);
end component;

begin
pb : pbup GENERIC MAP (N => 8);
PORT MAP(clk => clk_all,
rst => rst_all,
x => x_all, --i/p
fit => fit_all, --i/p
bfit => bfit_all, --i/p
new_bfit => new_bfit_all, --o/p
en => en_sig --o/p
);

gb : pgbup GENERIC MAP (N => 8) PORT MAP (clk_all , rst_all, en_sig, x_all, bg_all, new_bg_all);
end architecture;
----------
i'm using ModelSim SE 6.3

hope you find for me a solution for this error

A misplaced semicolon. In your code you had a semicolon after the generic map (N=> 8).

You also need to put a ); after "en => en_sig" to finish off the port map. You had that portion commented out.

pb : pbup GENERIC MAP (N => 8)
PORT MAP(
clk => clk_all,
rst => rst_all,
x => x_all, --i/p
fit => fit_all, --i/p
bfit => bfit_all, --i/p
new_bfit => new_bfit_all, --o/p
en => en_sig); --o/p);

Not the most useful error message, but the complaint is because the semicolon ended the instancing which occurs before the port map

KJ

what a ;

thanks alot Kevin..

for the ); its already there in a new line after the --o/p

thanks once again.. )