masoud.malekzadeh
Member level 1
I have defined a component as an adder how can i add rows of ROM ?
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But IMO the results were lackluster at best. It could very well be that I am just doing it wrong, but can't think of what to do to improve it. The best thing was just to say Fsck It! and hand optimize it. That did give me the performance I was after, and didn't take eons to synthesize. Because that's another gripe I have with retiming, take too frigging long. Again, I could be doing it totally wrong. So I'd love to have some pointers / reading material on how to do it properly!
That's not the code I posted, that's what you modified a bit and came up with.
Not a clue how you think that what you did is the only way to solve this problem
And now you've completely changed whatever the problem is to something completely different. You have many new undeclared signals and no definition now of just what you're trying to do.
Whatever that is supposed to mean...
library IEEE;
use ieee.std_logic_textio.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity adder is
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
clk: in std_logic;
result: out std_logic_vector(31 downto 0));
end adder;
architecture rtl of adder is
begin
result <= std_logic_vector(unsigned(a) + unsigned(b));-- when rising_edge(clk);
end rtl;
library IEEE;
use ieee.std_logic_textio.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use std.textio.all;
entity ROM is
port (
-- x_out: inout std_logic_vector(31 downto 0 );
-- x_in: inout std_logic_vector(31 downto 0 );
clk: in std_logic;
reset: in std_logic
);
end ROM;
architecture Behavioral of ROM is
type ram_type is array (9 downto 0 ) of std_logic_vector(31 downto 0 );
signal ram :ram_type;
signal i : integer range ram_type'range;
signal w:std_logic_vector(31 downto 0);
signal y:std_logic_vector(31 downto 0);
signal t:std_logic_vector(31 downto 0);
signal Prev_Sum:std_logic_vector(31 downto 0);
component adder
port (
a: in std_logic_vector(31 downto 0);
b: in std_logic_vector(31 downto 0);
clk: in std_logic;
result: out std_logic_vector(31 downto 0));
end component;
begin
process
FILE infile : TEXT is in "in_code.txt";
FILE outfile : TEXT IS OUT "out_code.txt";
VARIABLE out_line: LINE;
variable my_line : line;
variable int: std_logic_vector(31 downto 0 ) ;
begin
for i in 0 to 9 loop
readline(infile,my_line);
read (my_line,int);
ram(i)<=int;
write(out_line,int);
writeline(outfile,out_line );
end loop ;
wait; -- Waits forever
end process;
process(clk)
begin
if rising_edge(clk) then
if (reset = '1') then -- Something that resets the accumulated sum to 0
Prev_Sum <= (others => '0'); -- The accumulated sum
i <= 0;
elsif (i <= 8) then
Prev_Sum <= t; -- Save the updated sum
i <= i + 1;
end if;
end if;
end process;
w <= ram(i);
g1 : adder port map (a => w,b=>Prev_Sum,clk => clk,result =>t);
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tb_ROM is
end tb_ROM;
architecture RTL of tb_ROM is
signal clk: std_logic := '0';
signal reset: std_logic;
signal sim_complete: std_logic;
begin
reset <= '1', '0' after 10 ns;
sim_complete <= '0', '1' after 200 ns;
clk <= not(sim_complete) and not(clk) after 5 ns;
DUT : entity work.ROM
port map (
clk => clk,
reset => reset);
end RTL;