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Scheme to select one of the two clocks

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sun_ray

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Can anyone provide me a gate level diagram of a clock mux where depending upon the selection line either of the two clocks will come at the output? The two clocks among which one of them will be chosen are independent of each other and they may have different frequencies. The scheme is better if no glitches come at the output of the mux and only one of the clocks come at the output.
 

Since we do not know what is the phase condition of the other clock while use first clock there maybe a delay once first gets disconected and second gets in .is this ok..
the idea is to let the second clock decide (after getting request from mux) when to get in.
anyway what are the clock are they multiplication or division of each other ?
 

dselec

The clocks themselves do not have any relationship in terms of phase and frequency. There are two independent cloks and we need a gate level circuit diagram that can chose any one of them depending upon the value on the selectionl line. The selection line is one bit.

So the clocks are not multiplication or division of each other.
 

R u good with logic circuits ?
u did not reply my question about delay .
does it matter that there be some delay from ending job with one clock and starting with another ?
about glitch does your circuit work with logic level or rising/falling pulse ?
 

**broken link removed**
 
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    dselec

    dselec

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dselec:

I am not getting what you mean by delay here. What I want here is s scheme that will chose one of the independent clocks depending upon the selection line irrespective of the delay between the two clock cycles as it happens in a mux. You may include mux also in your design if you wish.

Regards
 

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