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VHDL STD_LOGIC_VECTOR (+ '1') vs UNSIGNED (+ 1)

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shaiko

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When adding std_logic_vector a logic '1' - I write:

some_std_logic_vector <= some_std_logic_vector + '1'

However,

When using the standart unsigned type , we should write :

some_unsigned <= some_unsigned + 1 -- we musn't use the inverted commas


What is the reason ?
 

it is due to function definition in library. related take a look into library you will find out why
 
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why are you adding with std_logic_vectors? those libraries are non-standard VHDL. Just use numeric_std (I know VHDL2008 does now allow this, but not with std_logic_unsigned/signed library).

But as above, its to do with the function definition. You can to do the same with the unsigned signal too, as long as you qualify it as an unsigned:

some_unsigned <= some_unsigned + unsigned'('1');

you should also be able to add this too (with non-standard VHDL library std_logic_unsigned)

some_slv <= some_slv + 1;
 
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shaiko said:
When adding std_logic_vector a logic '1' - I write:

some_std_logic_vector <= some_std_logic_vector + '1'
Click to expand...
So, you are still using the obsolete non-standard libraries.

In std_logic_unsigned, I think this operation is defined for both std_logic (one bit) and integer as the right-hand argument.
This means that this also should work:

some_std_logic_vector <= some_std_logic_vector + 1;

but I am not sure since I don't use that library.

Remember, '1' means just a single bit. If you want to add 2, you must write it as one of the following:
some_std_logic_vector <= some_std_logic_vector + "10";
some_std_logic_vector <= some_std_logic_vector + 2;

I don't know why I help you with this, because I think you should use numeric_std and not do any arithmetic operations on std_logic_vector.
 
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std_match said:
So, you are still using the obsolete non-standard libraries.
Click to expand...

Actually, VHDL2008 added numeric_std_signed and numeric_std_unsigned that act the same as the old std_logic_unsigned/signed
 
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I'm not using std_logic_vector...

The reason I mentioned it , is because I know that some_slv + '1' works while some_unsigned + '1' doesn't... I expected it to work the same way for both liabraries - and it doesn't.
 

shaiko said:
I'm not using std_logic_vector...

The reason I mentioned it , is because I know that some_slv + '1' works while some_unsigned + '1' doesn't... I expected it to work the same way for both libraries - and it doesn't.
Click to expand...

some_slv + '1' is std_logic_vector "+" std_logic
some_slv + 1 is std_logic_vector "+" integer

Each use of "+" must be explicitly defined in the library, so differences between libraries isn't strange.

I will not use numeric_std_unsigned and numeric_signed. I think you can only use one of them in any piece of code. You will get into trouble when you want unsigned and signed in the same entity.
I don't understand why they included this stuff in the VHDL-2008 standard. It makes the situation worse.
 
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shaiko said:
I'm not using std_logic_vector...

The reason I mentioned it , is because I know that some_slv + '1' works while some_unsigned + '1' doesn't... I expected it to work the same way for both liabraries - and it doesn't.
Click to expand...

Remember that std_logic_signed/unsigned was written by synopsys and not part of the VHDL standard. It contains a slv + std_logic function. They ignored the mechanics of VHDL to make life "easier" for themselves. There also wasnt much use for it other than the odd counter at the time because devices were small.
numeric_std was written by IEEE, and contains no unsigned + std_logic function, because that would be against the point of the strong typing system.

I will not use numeric_std_unsigned and numeric_signed. I think you can only use one of them in any piece of code. You will get into trouble when you want unsigned and signed in the same entity.
Click to expand...

And I doubt most people will use them either. But it is technically possible to use both, like its technically possible to use both std_logic_signed and std_logic_unsigned in the same file, it just becomes a chore specifying which one you mean (and probably confusing the hell out of the reader)

some_slv1 <= a ieee.std_logic_signed."+" b;
some_slv2 <= c ieee.std_logic_unsigned."+" d;
 

Strangely shaiko never mentioned explicitely which libraries he used in his code.
 

std_match said:
I don't understand why they included this stuff in the VHDL-2008 standard. It makes the situation worse.
Click to expand...

I saw this question on the VHDL newsgroup. The reply from someone in the standards body was that some people asked for it.
I think std_logic_signed/unsigned are now included in VHDL2008, but they are just wrapper packages for the new numeric_std_signed/unsigned
 

TrickyDicky said:
I saw this question on the VHDL newsgroup. The reply from someone in the standards body was that some people asked for it.
I think std_logic_signed/unsigned are now included in VHDL2008, but they are just wrapper packages for the new numeric_std_signed/unsigned
Click to expand...

Its because it's just stupid to force people to micromanage their code. It was a mistake when they first did it, and it's a mistake that they didn't find a way to fix this in the new version.

When I look at my code for unsigned, it's mostly counters. Past that, it's non-comparable unsigned (eg, addresses into circular buffers). It's just easier to:
1.) doublecast -- x <= std_logic_vector(unsigned(x) + 1); -- now x can be used EVERYWHERE else without any extra casts. Had x been unsigned, I would need to remember that fact, and convert it back to std_logic_vector everywhere its used.
2.) import at least std_logic_unsigned."+" into the design.
3.) re-write the "+", conv_integer, conv_std_logic_vector functions.

In the end, it doesn't matter. if you want to micromanage types based on "I used something resembling addition once", you can. If not, there are at least 3 options.
 

permute said:
1.) doublecast -- x <= std_logic_vector(unsigned(x) + 1); -- now x can be used EVERYWHERE else without any extra casts. Had x been unsigned, I would need to remember that fact, and convert it back to std_logic_vector everywhere its used.
Click to expand...
When do you need to cast from unsigned to std_logic_vector? I try to use unsigned/signed also for ports.
 

I try to use unsigned/signed also for ports.
Click to expand...
That's the better solution for signals representing numeric quantities, I think. A restriction for this approach comes from the fact, that vendor IP is mostly using std_logic_vector for ports, that clearly represent unsigned and signed numbers, e.g. DSP components. You can however change the port types to compatible signed and unsigned vectors in the component definition.
 

So...you can use SLVs together with UNSIGNEDs in the same entity ?
 

shaiko said:
So...you can use SLVs together with UNSIGNEDs in the same entity ?
Click to expand...

If you use numeric_std, you can mix unsigned, signed and std_logic_vector (and all other types) as you wish in one entity. numeric_std takes advantage of the strict type handling in VHDL.

std_logic_unsigned/signed instead overload operators on std_logic_vector, so it is not easy to mix them.
 
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Is it possible to connect SLVs and UNSIGNEDs signals between entities ?
 

shaiko said:
Is it possible to connect SLVs and UNSIGNEDs signals between entities ?
Click to expand...

Yes, but you need to cast somewhere. You can cast port connections in the instantiation.

FvM mentioned that it is possible to change port type in the component definition, but I have never done that.
 

FvM mentioned that it is possible to change port type in the component definition, but I have never done that.
Click to expand...
I have previously done it in Altera Quartus (and a parallel Modelsim simulation, if I remember right). I 'm not sure if it's an assured feature of the VHDL standard or only possible due to relaxed type checking.
 

FvM said:
I have previously done it in Altera Quartus (and a parallel Modelsim simulation, if I remember right). I 'm not sure if it's an assured feature of the VHDL standard or only possible due to relaxed type checking.
Click to expand...

Quickly having a look through the 93 LRM, I canot find a specific reference, but I know that direct instantiation would fail. I suspect the success by using a component is down to Quartus (and modelsim) being required to compile mixed language designs, and needs to map VHDL -> Verilog -> AHDL, so just converts everything to std_logic or other language equivolent.

It could also be that unsigned and std_logic_vector are "similar types", so conversion is trivial.
 

TrickyDicky said:
Quickly having a look through the 93 LRM, I canot find a specific reference, but I know that direct instantiation would fail. I suspect the success by using a component is down to Quartus (and modelsim) being required to compile mixed language designs, and needs to map VHDL -> Verilog -> AHDL, so just converts everything to std_logic or other language equivolent.
Click to expand...
Actually you perform the conversion right in the port map when instantiating the component, no component declaration changes are needed. As an example, here is how you would connect up std_logic_vector signals to an entity that has unsigned input/outputs

Code: 
dut : entity work.widget
port map(
    inp_unsigned => unsigned(some_slv),	-- Convert an input
    std_logic_vector(out_unsigned) => some_other_slv); -- Convert an output

It could also be that unsigned and std_logic_vector are "similar types", so conversion is trivial.
Click to expand...
No, they are not similar (assuming that you mean by 'similar' is what VHDL refers to as 'closely related types'). unsigned and std_logic_vector are different base types so VHDL does not allow them be directly assigned, they must be converted. Typically, this can be done as:
some_slv <= std_logic_vector(some_unsigned);
But as I've shown, this conversion can also be specified directly in a port map to an entity as well.

Kevin Jennings
 

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