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seeking help in verilog code

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ranga4a2

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i dont know how to write the synthesizable verilog code for the remainder or modular division operation ..

can any one help me in this matter.
 

Dividing is the same as multiplying.example:

I have this : 0001, if I'd want to divide by 6:
count up 'till 0110(CNT <= CNT +1), then make an if x = "0110" then div6 <= '1'(this is written in VHDL, dont know how it should be in Verilog)
 

hi,
you can write synthesizable code for any language if you have hardware for it.
First work on hardware as reminder and modular operator are not synthesizable ,
then it will be easy for you to describe it in Verilog.
 
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