shaiko
Advanced Member level 5
Hello,
I'd like to simulate open drain pulled up ports in my testbench.
For example: I2C clock and data inout ports are outputed as high 'Z' an then pulled up to a '1' by a pull up resistor to achieve a "wired and".
In my simulation, I want the outputs that get <= 'Z' to be resolved as a logic '1'.
I know that the correct way to do it is write a resolution function. But I don't know how and where to write it...please help me with the VHDL code.
---------- Post added at 11:07 ---------- Previous post was at 10:52 ----------
------------------------------------------
function resolve_logic (drivers : in logic_array) return logic_level;
begin
for index in drivers'range loop
if drivers(index) = L then
return L;
end if;
end loop;
return H;
end resolve_logic;
------------------------------------------
I found the function above but I don't know where to put it so it would work and pull the 'Z' to '1' and resolve '0' and 'Z' to '0'
I'd like to simulate open drain pulled up ports in my testbench.
For example: I2C clock and data inout ports are outputed as high 'Z' an then pulled up to a '1' by a pull up resistor to achieve a "wired and".
In my simulation, I want the outputs that get <= 'Z' to be resolved as a logic '1'.
I know that the correct way to do it is write a resolution function. But I don't know how and where to write it...please help me with the VHDL code.
---------- Post added at 11:07 ---------- Previous post was at 10:52 ----------
------------------------------------------
function resolve_logic (drivers : in logic_array) return logic_level;
begin
for index in drivers'range loop
if drivers(index) = L then
return L;
end if;
end loop;
return H;
end resolve_logic;
------------------------------------------
I found the function above but I don't know where to put it so it would work and pull the 'Z' to '1' and resolve '0' and 'Z' to '0'