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OK. Writing one good testbench is a difficult task for one big design. It needs more efforts to acomplish this task for each detail. Is it one way to record all histroy in the actual debugging??
I often use the signal tap or reval to debug my fpga. However I find the effency is a little low with my expactation? For every revision, it needs a lot of time to re-compile the all project and generates the download file. Does anyone give me a good way to debug the complex fpga??
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