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Recent content by zyphor

  1. Z

    Constraining Multiple clock design

    pls find this issue in Prime time guide
  2. Z

    Looking for materials on die size estimation in digital core

    Re: die size estimation I think you should have knowledge on : 1. gate counts of the design 2. Memory size 3. I/O 4. Power ring 5. Power strap and (1+2+3+4+5)/70%= rough die size
  3. Z

    Formality problem: top/sub module issue

    Re: fomality problem You must pay attention to the constant register that be removed by DC. The removed registers may cause many failing points, but in the module level it is easy for the tool to analysis RTL code and no error occurs
  4. Z

    What is a good core utilization percent ?

    Re: Core utilization pretty good design, of course you should address die size, if die size is small ,the utilization should be high.
  5. Z

    how do we diffrentiate FPGA and CPLD

    CPLD's route resource are all global resource , can garentee the delay , but have the resouce is limited FPGA has two kinds of route resource, local and global.
  6. Z

    How to decide clock synthesis parameters such as latency and skew?

    Re: question about cts it is determined by you register number. if one stage clock buffer can drive 12 clock buffer node, you can computer how many stages it needs to drive the registers in your design.
  7. Z

    what different between post-sta and sign-off sta?

    I think: there is no difference . sign-off sta must be post-layout sta. When layout is done , the spef parameter file is extracted and the sta is done to decide whether the layout is timing ok for tapeout. what is the post-layout sta aim to do is also to determine whether...
  8. Z

    use which tools to insert scan chain?

    scan insertion mentor synopsys's scan insertion tool: dft compiler, bsd compiler is easy to use, but synopsys's membist tool is rather bad, just better than do it manully. Mentor's membist tool: memory Architecture is really excellent and its scan chain generator :fast scan is also excellent ...
  9. Z

    why avoid using tri devices?

    I doubt that tri-state bus will consume more power than corresponding Mux circuit? Can someone give more specific analysis?
  10. Z

    some questions about Astro!

    before CTS, the clock is ideal for all flip-flops so that the result is not precise. After CTS you should add set_propagated_clock in the sdc file to specify the real clock network latency for all clocks.
  11. Z

    FIFO depth using in clock domain crossing

    how to calculate fifo depth if the two clock has no relationship, minimum depth is 4 words, you may also see some design is 3 words, but it is special design, not for general case
  12. Z

    How to identify tri-states in DC

    Re: Tri-states in DC you can list all references in the design, and find tri-states device in your library.
  13. Z

    How to replace designware cells in the netlist

    you can optimize your algorithm from architecture level and make DC synthesis it easily .
  14. Z

    Path timing report in DC

    at first you should have memory's timing model, and in common it is in the .lib file of your memory. Then you can check the timing of the register linked to the output of the ram to find the read timing .

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