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Recent content by IntuitiveAnalog

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    Wide Swing PMOS Cascode Biasing

    As I mentioned, M2's saturation condition is Vov2<= |Vth1|. The drain voltage of M2 and gate voltage of M1 is provided by a current source. The full biasing circuit is attached in the picture below. It looks like, at fast hot corners, either M1 or M2 could be kept in saturation and the other...
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    Wide Swing PMOS Cascode Biasing

    Hello, I would like to know if someone has designed a wide swing PMOS cascode biasing circuit (as attached in the picture) in 16nm FinFET, especially for IO devices having 1.8V supply. I see that theoretically it should be possible to keep M2 in saturation as long as Vov2<= |Vth1|, but...
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    Input stage in a reduced input swing sense amplifier flip flop

    In a sense amplifier based flip flop as shown in the figure, if the data input (D) and clock input (Clk) have Vdd/2 (half the supply voltage) swing, then will it necessitate to use complementary structure instead of the shown structure (i.e. PMOS input pair and PMOS tail transistor, along with...
  4. I

    Input impedance simulation of a chopper amplifier

    Hello Everyone, Has anyone simulated input impedance of a chopper amplifier using Cadence spectre? I have experience of using pss and pac analysis but I am not sure how I can find input impedance of the amplifier as shown in the picture below (where chopper is similar to a mixer)::
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    Noise calculation for common source amplifier

    In switched type of circuits, one should generally use pnoise analysis. Simple noise analysis may not give you expected results.
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    Signal Acquisition with high sampling rate

    Yeah I have seen some of the boards from National Instruments, but have not come across such high sampling rate yet. - - - Updated - - - Yes, that's the requirement. What exactly do you mean by it?
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    Signal Acquisition with high sampling rate

    Hi everyone, I have a PWM sort of wave having frequency of few kHz and 0-10 V amplitude, which I need to acquire (for post-processing with MATLAB) using acquisition board/kit with a high sampling rate of the order of a few GS/s. I will be thankful if anyone could give an idea about acquisition...
  8. I

    FET intrinsic gain characterisation

    Hi everyone, I am characterizing a Field effect transistor with a verilog A model using spectre. I want to plot gmro (intrinsic gain) vs vds. But the problem is that, the model does not store gm or gds values in dc operating points. Is there any test bench from which I can extract gmro vs vds...
  9. I

    Implementation of HR neuron model using analog computer technique

    Does that mean I need to use lower capacitor values? One more thing which I doubt is the DC level of the signals. Can you please comment how DC levels should be adjusted?
  10. I

    Implementation of HR neuron model using analog computer technique

    Hi BradtheRad, So what could be the reason of not getting the expected output?
  11. I

    Implementation of HR neuron model using analog computer technique

    Hi Everyone, If there is anyone who has experience of designing analog computer based circuits , please have a look at the code and the circuit . I will be extremely thankful if anyone could suggest me what might be the problem.
  12. I

    Implementation of HR neuron model using analog computer technique

    Hi FvM, I have tested models of opamp and multiplier individually and they are working fine. The obtained and expected output is shown in the attached figure.
  13. I

    Implementation of HR neuron model using analog computer technique

    Hi Everyone, I am simulating(using HSPICE) HR neuron model using analog computer technique but I am not getting the required response. If anyone can figure out what might be the problem , I will be extremely thankful. I am using ALM124 model of opamp and MLT04 model of multiplier. ***HR***...
  14. I

    Biasing of Multiplier Circuit

    Hi,
  15. I

    Biasing of Multiplier Circuit

    Erikl , First of all I am thankful to your response. Actually I have taken this design from an IEEE transaction. Author has taken Vdd as 1.5V in 0.35um process.
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