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Probably I'll follow that way, I have just used this approach last week in order to solve a similar problem. Thanks!
Other suggestions?[COLOR="Silver"]
---------- Post added at 12:39 ---------- Previous post was at 11:41 ----------
Sorry, but as I told you before I'm using a CPLD, so it can...
I'm working with two devices. One of them works at 50 MHz and the latter at 100MHz. Substancially from one side I should take data at 100MHz and translate them to 50MHz, and do the opposite on the other side. I should implement this bridge inside a CPLD, do you see any problem? Suggestions about...
...in the second case you mean use something like a page register?...
But now I'm thinking... maybe I'm lucky because Device A & Device B, use a clock frequency double than the memory, so I could form a 26bit address in 2 clock cycles, and let the memory work normally with the maximum frequency...
I have to solve the following problem ...
I need to address a 1Gbit memory (with 26 address lines), but the device in charge to do this operation has only 24 address lines. I read somewhere that usually in these cases the problem is solved by using a portion of the data bus in order to decode...
Finally I found a behavioral model with some examples and a feedback line on wich I can receive information about what I'm doing. In this way I understood definitively how this prom works, and more or less I've been solved all my problem, now I have just to fix last issues and be sure that I'm...
I've already done all you suggested. Nothing on the manufacturer's web site, and no answer from their tech support. This Prom is it just a BGA :-) and the issue about I'm in trouble, it's in the "simple" read/write operation
I mean, if I can use a behavioral model, provided by a feedback...
I'm getting crazy with a Prom memory. I'm trying to interface it at an FPGA, using a controller implemented inside a CPLD. However I've found ambiguous information on the datasheet, and using Chipscope, I saw that I'm so far away from my goal. Because of that I would like to find a Behavioral...
If I'm not wrong, I remember the possibility to use an FPGA in master mode, in order to configure another/other FPGA/FPGAs using the SelectMap Interface. It is right?
Someone could please indicate some documents about what I'm looking for?
I can not find anything :-(
I already have three different signals (two from A the separate input and output, and one from B)
now you mean something like that?
process(s,inp)
begin
case s is
when '0' => op <= inp_A and bus_enable <= enable_A;
when others => op <=inp_B and bus_enable <= '1';
end case;
end process;...
This is my question...
I have two modules and they share an I/O bus of 16 bits.
The first module, that we can call module A, needs to use all 16 bits in bidirectional mode.
The second module, that we can call module B, needs to use just 8 bits in output mode.
Which is the best solution in...
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