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Recent content by zlop

  1. Z

    Which language to use for DSP, C or Assembly ?

    c or assembly language C, trust me, u won't regret. Almost anywhere in DSP or Micro-Controller designing need to use C.
  2. Z

    Is there a uniform DCC format for diff SDH devices ?

    Hi, everybody: I met a trouble when reading the protocols of SDH -- that is I didn't find any rule about the format of DCC in the SOH thruout the protocols. I want to ask: Is there a uniform DCC format for diff SDH devices ? Can the diff SDH devices which are from diff vendors or manufacturers...
  3. Z

    Is possible for hold time to be 0ns??

    I agree with salma ali bakr.
  4. Z

    What's the advantage of writing VHDL that can be recognized

    Re: What's the advantage of writing VHDL that can be recogni In VHDL, the CASE statement's default branch is NOT imposed by the IEEE standard. It's "SUGGESTED". In synthesisable coding style, the process method of "default" depends upon the synthesis tool you use. Some need it, and some dont...
  5. Z

    How to simulate VHDL code that write an output to a screen?

    VHDL Questions A TO Q1: U need to write a hierachical testbench to view whether it is successful. It's complex. A TO Q2: It is a question of CODING STYLE. Also, it cannt be explained exactly here.
  6. Z

    Need help: LED display for V-II

    If you have many LEDs, due to the FPGA's current limit, don't connect them to the same bank--you can see the data sheet for further information. I suggest you to use special LED IC to design your project. Good luck!
  7. Z

    Which FPGA is better for ASIC verification?

    Which is better? If ur design is sensitive to the cost, I believe altera is good choice. By the way, the tools altera provides is more convenient to use, in my opinion. ^_^
  8. Z

    Can the FPGA be used to implement an ethernet switch ?!

    vhdl ethernet switch It's based upon the performance goal and the scale ur design is required for. U can go to the www.opencore.com to get some free core and datasheet for Eth switches. Good luck. Added after 4 minutes: Sorry, it's www.opencores.com. My fault.
  9. Z

    VCS, NC-Verilog and Modelsim, which is the best simulator??

    I use Modelsim to do the sim of RTL level and for the functional verification. It looks very good!
  10. Z

    Is dualport ram much more costly than singleport ram asic?

    tsmc 0.18u bitcell Of course, it depend on the num of the port and width of banks.
  11. Z

    serial versus parallel data transfer

    serial vs parallel data Member puviarasu is right. But additionly there is another thing he(she?) doesn't notice: Nowadays, clock fre is a most important thing to determine the performance of a sys. Due to the EMI reasons and the cross noise between wires, the SERIAL is better than the PAR.
  12. Z

    help me in buying a FPGA or CPLD kit

    Spartan III is enough, it's depend on your system's reqirement, both nowadays and for future.
  13. Z

    Waiting suggestions about optical network study

    Hi, I'm a new guy to this field, but I have a job of finishing a ATM pon's MAC controller(using FPGA, of course the design is to complete parts of total functions, just ATM cell's management). I'm a RTL experienced designer but a fool to networks. Who have some exp on those things? Please give...
  14. Z

    Sometimes I am confused! Could someone give some suggestion?

    You're lucky enough. Think those guys who are at the bottom of a group. You will find the place and the salary you get may make somebody else envy. Think more about the actual situation, and if you go to do maket, all will begin from zero. Is it you want? Too expensive.
  15. Z

    About Power Plane in double layers

    Ur board is 2 layers and because this,it can't be used in very high freq. If ur board need to run in high freq, try other type, eg. 4 layers .There is no good solution for 2 layers.

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