Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Smartmodel question
Does anyone have experience in simulate using smartmodel and design using xinlinx isev4. I want to construct a board level simulator enviroment using these two tools. I need using smartmodel's 386 model and fpga designed using xinlinx. How can i do this?
Thanks above everyone.
Yes we have much people doing this project.And i am charging EDA for this project. So i am much interested in such asic design flow. Say truely i am not worried about the IA64 architecture complexity.We have great man for design this. The compiler question is too. Now i...
Thanks asic. I will be glad to think through sun's cpu .
BTW anyone can point some best tool to design cpu ? If i buy i will share with everybody here.
I am not joker.
I am seriously. If someone is interested in helping me pls pm me. Now we have experience for developing chinset about 4 million gates and want to do more. Now i am new for design cpu and want to know the difference between chipset and cpu. I want to know the basic for design...
First thanks for gabby.
Now i am involving in designing a real more complex cpu than embedded cpu. This is designed compatible for intel IA64.So now i want to make friends with those who have made work for intel or ibm.I need to know how they design such cpu .
design cpu
Now i have a preject to design a 64 bit cpu . I have some question to ask whom have experience in doing that.pls pm me if you have experience with that and glad to help others.
Tool for asic
Here is my list for my last finished work :
synopsys dc,primttime,formality,vcs(like it),
transeda cover
asic vendor's floorplan tool and p&r tool and gate sim tool.
I have two question :
1.Have anybody experience in designing asic using ip core . And what kind of core do yur use.?
2.I want to summerize our previous design work .And i want to make some ip core for next usage.For example fifo and control unit.
Which tool do i need?
Any comment will be...
Yes. We also will let company sales manager to introduce their products.But they are salers not engineers.And i think this place will be more open and accurate by yours friend.
Much thanks for kunjalan.For some reason I am sorry I can't tell more clearly for my project. I can only say this is about 0.1um level design . But if someone have experirence in design for 0.1um pls let me know. I now just have two question :
1.delay model in 0.1um.Is the model much different...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
