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Hi cruschow:
great thanks for your immediate response!
Best wishes
Hi ZekeR:
the paper is discussed about the ripple regulators which use the hysteric comparators, and it is quite exist some ripple regulators that does not use a hysteric comparator, such as MC34063, and what do you think...
Hi crutschow:
Thanks a lot for your kindly help!
It is easy to understand from the bode of LOOP gain that the higher frequency the lower gain which is able to reject the amplify of the ripple voltage with the switching frequency.However, from the expression of ripple voltage，the higher the...
Hi:
why set the loop bandwidth 0.1~0.2 of the switch frequency in DCDC ?
and i got two reasons: one is based on the sampling theorem, that bandwidth must smaller than half of the switch frequency ; and the other is the noise consideration.
Best wishes!
Hi Varunkant2k:
Thanks for your help.
and the High impedance you mentioned is the Rout of the EA?
And now I am confused about the function of EA, usually, its function is described as "amplify the error signal ", however, after adding the compensation net, the gain is determined by the ratio...
why the voltage mode compensation use external capacitor which connects between error amplifier output and inverted input , and the error amplifier is opamp with buffer stage but not gm amplifiler (OTA).
As we know the current mode is gm amplifier ,whether the voltage mode can use OTA or not , why ?
Hi kerim:
Thanks for your advising very much!
Jimmy
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Hi Fvm:
What do you mean " an additional peak current detector controlling...
Hi Kerim:
thx for your minding.Just like you say "the the maximum duty cycle of the main switch is equal to the duty cycle of the clock at the AND input"
and after simulation i find out the duty at the AND input is discontinuous in a cycle, changing with the ripple of Vout,
so can you tell me...
there is no EA in the LOOP and the feedback voltage is directly given to the COMP, and the chip can be used in BUCK , BOOST AND buck-boost
after analysis I just find out : the working frequency is fixed by clock, and the duty is determined by the Vfb and Vref during one cycle，and i want to know...
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