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Recent content by zhancangF117

  1. Z

    Questions about 1.5bits/stage in pipeline ADC

    There are two types of CMOS TG switch: 1. Symmetric TG, with the same W of both P,NMOS, less suffered from charge injection 2. Asymmetric TG, with approximately un/up ratio W of P,NMOS, less coupled with input. Size depend on your application, larger W/L , small ron. tPHL=tPLH=(ronN//ronP)Cload.
  2. Z

    How to use Cadence Tools to simulate PLL Phase noise

    Hello, everybody I want to simulate a PLL design's phase noise, could anyone help me, or offer some reference? Thanks a lot!
  3. Z

    Problem with defining DNL of Nyquist ADC

    INL/DNL of Nyquist ADC ADC DNL shoud not be less than -1LSB
  4. Z

    Need value for Lambda

    i am not sure about 0.25um but i konw lambda is inversely proportional to channel length. for 0.18um lambda-n is about 0.77@0.18um lambda-p is about 0.57@0.18um
  5. Z

    What is the METTOP layer?

    What is METTOP layer? METTOP is top metal
  6. Z

    is it good using Deep N-well for Analog circuit?

    deep nwells are usually used in RF chip design to protect device from substrate noise and inject noise to substrate. but it will cost a lot , for TSMC this layer will cost about $100
  7. Z

    How to start learning DAC?

    under 7bits R2R ladder above 7 current source matrix
  8. Z

    What is Polygon and what is path in IC layout?

    IC Layout Polygon is used to draw complex shape of metal or poly. Path usually to draw bus or interconnection straight.
  9. Z

    What are the process design rules?

    Process Design Rules to guarantee your design fabrication reliability provided by fundry
  10. Z

    How can i test INL/DNL

    inl and dnl measurement @ maxim dallas's website. ADC exactly, DAC is not sure,but it's easier than ADC
  11. Z

    [Help] How to learn Cadence?

    I recommend you get some advice or short introduction from your collegues. I do not think the online documentation is most convienent and fast way to getting used to cadence.
  12. Z

    Process Information for 0.18um

    Uo of NMOS is about 0.0459 m^2/Vs Uo of PMOS is about 0.0109 m^2/Vs vthn is about 0.445 (TT) vthp is about -0.438 (TT) for 1.8v MOSs
  13. Z

    Looking for documents about Pipeline ADC design

    Pipeline ADC design You can find some useful thesis of this site. P.R. Gray and his students **broken link removed**
  14. Z

    What factors should be considered when choosing an op-amp?

    Op-Amp Selection most on its application and structure Slew rate bandwidth

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