Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Zampradeep

  1. Z

    [SOLVED] Verilog clock divider to go from 2.048MHz to 2Hz

    ..O sorry use 20 binary bit counter..or 10 bit binary counter cascaded with 3(0-999) digit bcd counter..1024*1000=1.024m.....2.048m/1.024m=2 hz
  2. Z

    pwm code in vhdl help

    ..Tricky bro i never asked u to give me code.... just seeking hint where i am going wrong..circuit goes like this serial data of 100 hz clock of 1khz and (0-10)counter 4 bit comparator... Reference->-----comp Clock->counter->comp if counter>reference dout=0 reference of signal of 0010 and...
  3. Z

    pwm code in vhdl help

    ..Plz bro help..logic is whenever serial data changes state it enters into to the process and at every clock pluse of /10 counter .signal count is incremented and condition is checked..
  4. Z

    pwm code in vhdl help

    ...1st sorry its my 1st post so didnt know that we have to use tags for code...@tricky bro then what should i use if instead of while...is there any other itiration statement keyword...
  5. Z

    [SOLVED] Verilog clock divider to go from 2.048MHz to 2Hz

    ..Just use a 10 bit or (0-1024) binary counter..carry output of 10th bit is 2 hz signal....
  6. Z

    pwm code in vhdl help

    ..hi guys..others project is time code generator on fpga and generated time code ....now have to do pwm....here is the code i wrote but not getting output...in code i used /100 counter as actual serial data and /10 to compare it and change duty cycle.....i.e each serial data pluse time=10 times...
See more

Part and Inventory Search

Back
Top