Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: what's different between Floorplan Compiler and JupiterX
I thinks is very similar!!
Just as same as Saturn/Astro & PC for plasement stage.
SomeBody say that Saturn/Astro can get better solution for high cogention soultion and Pc get better solution for timing issue.
It is different...
I use set_ideal_network for HFN in DC.
Because some of HFN is general singal (not set,reset)
DC will change my structure inserting Buff/Inv.
And when I use Apllo to CTS for HFN, puge Buff/Inv to cause funtion error
How can I solve it.
>Spice backannotation may be too slow. The popular flow is to extract >parasitics after IP merging to obtain a SPEF file. And then by using an >advanced timing delay calculator, a SDF file can be generated for your >post-layout simulation.
>Complement for linuxluo's gatelevel simulation.
I have one problem.
When I use cell_based design flow, I have some macro.
When I pre-simulation RTL-code , I can use behavior model for macro.
But I want to post-sim for SDF back-annotation, how can I treat it?