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Recent content by zackwang

  1. Z

    soc encounter training material

    Why I cannot down from Worshop' Link? It seems file://??? Anyone upload Data ?
  2. Z

    looking for Floorplan Compiler in pdf

    synopsys get Avant! so they has the same product Jupiter. Somebody say Synopsys will left FPC ,but FPC will be improve from Jupiter. Maybe later 2003.12 FPC will change much.
  3. Z

    The design_vision GUI crashes in 2003.06 version

    Re: design_v*s*on 2003.06 It seems tools bug. You can use design_v*s* -no_gui When you enter command line. you type start_gui I can work it using this method
  4. Z

    what's different between Floorplan Compiler and JupiterXT?

    Re: what's different between Floorplan Compiler and JupiterX I thinks is very similar!! Just as same as Saturn/Astro & PC for plasement stage. SomeBody say that Saturn/Astro can get better solution for high cogention soultion and Pc get better solution for timing issue. It is different...
  5. Z

    What CTS method can reduce clock skew in Apollo?

    clock skew in Apollo What CTS method about generated clock & overlapp & gated clock can reduce skew?
  6. Z

    Help me with Chip Implement flow from RTL to GDSII

    Chip Implement flow EDA tools is very complex. Anybody have good idea for Chip Implement flow from RTL to GDSII. I use synopsys flow DC=>PC=>astro (primtime)
  7. Z

    Good book on ASIC design - request for resources

    That's very good. You can find 2nd version in MCU. But I want to get 3nd . Anyone has it,and upload it.
  8. Z

    Apllo to CTS for HFN, puge Buff/Inv to cause funtion error

    I use set_ideal_network for HFN in DC. Because some of HFN is general singal (not set,reset) DC will change my structure inserting Buff/Inv. And when I use Apllo to CTS for HFN, puge Buff/Inv to cause funtion error How can I solve it.
  9. Z

    About Cell_based Design flow

    >Spice backannotation may be too slow. The popular flow is to extract >parasitics after IP merging to obtain a SPEF file. And then by using an >advanced timing delay calculator, a SDF file can be generated for your >post-layout simulation. >Complement for linuxluo's gatelevel simulation. But...
  10. Z

    About Cell_based Design flow

    I have one problem. When I use cell_based design flow, I have some macro. When I pre-simulation RTL-code , I can use behavior model for macro. But I want to post-sim for SDF back-annotation, how can I treat it?
  11. Z

    Many online e-books repository

    Many online book https://www.edatoolscafe.com/EDATools/EDAbooks/
  12. Z

    How can I get Model from HardMacro to put it together to sim

    From RTL-cod I can use SDF for backannoation. How can I treat to H.M. to whole Chip ?

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