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Recent content by yyy963741tw

  1. Y

    Run Veriloga demo in hspice 2013.03-SP2 error

    I run the demo file "resistor.sp" from /usr/cad/hspice/cur/hspcie/demo/hspice/veriloga have this error: and the "resistor.valog":*pvaE*please invoke hspice script instead of binary I don't know how to solve it? I run other spice file without veriloga module successfully
  2. Y

    Analog Design System(ADS) verilog_a_Tutorial_PSFETCV error

    so i should copy the veriloga code into netlist? I mean this work provided by program tutorial . It Should be able to simulate normally . But it can't
  3. Y

    Analog Design System(ADS) verilog_a_Tutorial_PSFETCV error

    I am sorry to mistype the word. how could i inculde th e model this tutorial example workspace should not already fininshed?
  4. Y

    verilog ams simulation

    What program do you use to simulate VerilogA?
  5. Y

    Analog Design System(ADS) verilog_a_Tutorial_PSFETCV error

    I simulated the example of veriloga tutorial workshop but with error message that : Error detected by hpeesofsim during netlist flattening. `psfetv1' is an instance of an undefined model `psfetv'. How can i solve it?
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