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Hi,
When running RTL simulation, is there any method that can enable the Read/Write of physical memory of the compute.
For example, for a given physical memory addr: 0xD0000000，can I R/W it in my test bench when the simulation is running? How to make this?
Thanks.
You need speicfy which PIN or Port this clock is mounted on.
In DC (synopsys Design compiler), there is some command like: get_pins "/designs/TOP/ports_in/CLK" to get that port or pin.
Or you can "man define_clock" in RC tool to get help and see some examples.
There are two kinds of violations in DC/PT.
1): Timing violation, which can be reported by report_timing
2): design rule violation. Such as your example: max_transition / max_capacitance violation. If you are doing PT just after synthesis, you can ignore these violations. If you are doing sign...
I think you may need the "get_cells" command and use the "-filter" option. Please "man get_cells" for detail.
Or you can write a TCL script to do it, using the DC/PT "attribute".
The clock gating hold violation is usually because: the clk_gate_enb reach the gating cell too fast than the clock signal.
So, of cause you can add buffer on the clk_gate_enb path to eliminate the hold violation.
(Assume the clk_gate_enb and clock signal are SYNC to each other)
1): fed the input address (input from the top wrapper) to the two rom.
2): decode the highest bit (bit[15] of input address), along with input rom_ce to generate rom_ce_0 and rom_ce_1.
3): According to the rom read command to dout cycle delay, delay the rom_ce_0 and rom_ce_1 some cycles, used to...
I think you need something like the following (using the attribute of each cells):
get_cells -hier -(other options you want) -filter "is_sequential == true". // you'd bettern use "man get_cells" to get detailed description on ''-filter" option
big transition --> big setup requirement --> violation.
You need check why there is some big transition. Maybe SI problem, or some problem in the extracted RC file.
I think it's unable to meet both setup and hold for such, if you using usual library cells. And it's also un-reasonable for the real DFF to have setup and hold both equal to 0.
Hi, Please try the "man write_file" command (write_file will replace write in the future).
Then the default write out format will be "ddc" format.
So you may:
1): write_files -format ddc -hierarchy -output $active_design.db
Or:
2): read_ddc or read_files -format ddc.
For any command, you can...
Hi, I think you need try the following:
1:
set search_path [list ../../XFAB018 ../RTL ./DB_SV]; ## not "/DB/SV
And designer always add the directory you invoke DC to the search path: set search_path [list . ../../XFAB018 ../RTL ./DB_SV];
2: Modify your read_db command. read_db...
Try to copy (or link) the fulladder.db and fulladder_npp.db to the directory where you invoke dc_shell.
If this works, you need check your "set search_path" command.
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