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Recent content by yung2002

  1. Y

    VHDL ------- viewing variables

    You can set some monitor signals during debug, then assign the variables to the signals,view the signals in modelsim waveform window.
  2. Y

    VCS, NC-Verilog and Modelsim, which is the best simulator??

    Modelsim and nc-verilog
  3. Y

    Howto add signals into SIMVISION with tcl command?

    1.Add the following task in you testbench initial begin $shm_open(wave_directory_name); $shm_probe("AC"); end 2.run ncsim, then type these tcl command: database -open waves_directory_name probe -create top_module_name -depth all run For more information,pls reference to ncvlog.pdf
  4. Y

    new link about netseminar

    thanks
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