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I am doing a mixed-signal design, the thing I am trying to do is to synthesize the digital part using standard ASIC flow and merge the digital layout with the analog layout in Virtuoso.
I got some standard digital cells from Artisan, they also provide a GDS2 file containing the physical...
LVS for digital design
I am designing a mixed-signal circuit
the digital part is implemented using Verilog, synthesized with DC and the backend is done with SOC encounter, now the problem is how to do LVS
The standard cell vender gives us a CDL file for LVS, in which it defines the sizes of...
Thank you, bloodemon
But the problem is that, if I use a capacitor for loading, the nodes of output don't have right biasing
My mentor told me to define the output resistor with normal resistence value in DC, but infinite otherwise. While seems Spectre doesn't have this ability?
For linearity...
Hi, I am a beginner in analog design, and I am trying to build a folded-cascode opamp,
While I found in the simulation results that the linearity is poor, there is 10% difference of the gain between the maximum input and input ten times lower.
Is there any suggestion on how to improve?
I have...
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