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Recent content by yttuncel

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    Altera Cyclone III USB or RS to HSMC Card?

    Hello, Basically I am developing a GUI to represent received data on a display. I have successfully implemented everything FPGA related except the input part. Ive been thinking of using SPI but the connector on Altera Board is HSMC and I have not used it before. Is there any USB to HSMC or RS...
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    Bitmap Rotation using VHDL

    The dots im talking about are shown here: https://www.datagenetics.com/blog/august32013/index.html They are due to the sine and cosine producing noninteger results and these results cause the destination not be mapped 1:1 to source. But inverting the rotation matrix solves the issue , just like...
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    Bitmap Rotation using VHDL

    After hours of working I concluded so :P This method is easy to understand but shearing the image wrto its centre is a rather hard thing to do. I can now rotate the image by shearing, but I need 1000x1000 canvas to rotate a 200x200 image by 75 degrees. So it is definitely not logic and memory...
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    Bitmap Rotation using VHDL

    Thank you for the answer. To me rotation by shear is more logic friendly as it calculates a shear amount for the whole line and places pixels accordingly. The other method needs to calculate where each pixel should map to, so it needs more computations on the paper. I've been doing some matlab...
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    Bitmap Rotation using VHDL

    Hello, In my current project I hold an image inside a ROM and when asked, I copy the content into a frame buffer which is read by the monitor. I can successfully copy and show the image on the screen. Now I am adding something new. The image will be rotated by x degrees (input) before being...
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    VHDL How to use TFP401 on a daughter card

    IMPORTANT UPDATE/QUESTION: Do you know how I can update the EDID information that is stored in the eeprom on the daughter card? I updated the edid from BITEC website but when I view the EDID contents with monitor info view 1440x900 is still not present. This is why the monitor does not support...
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    VHDL How to use TFP401 on a daughter card

    I know about the timings but I was not sure how the receiver worked. I think I got over the issue, but now I am facing a new one. I connected the receiver to my computer's GPU (as an extended dual monitor setup) and transmitter to monitor. Computer recognizes the display automatically but it...
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    VHDL How to use TFP401 on a daughter card

    No problem, thank you for your response. I couldn't find any vhdl design on the web that is using a vga/dvi/hdmi input/receive. Could you please help me find something similar to my project, I don't know if I need to google a specific word/phrase.
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    VHDL How to use TFP401 on a daughter card

    I am basing my design on a reference design that is working (receiving from TFP401 and transmitting from TFP410), and that design uses that LLC signal as clock just as I explained. However, I also have access to those DVI-A signals you are speaking of, and I know what they are responsible for...
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    VHDL How to use TFP401 on a daughter card

    Doesn't the card do those tasks itself and outputs a LLC signal ready to use? I am using that LLC signal, that is the pixel clock of my received video. I am using that clock both as a system clock and pixel clock for transmit part. I am using a similar controller to this ONE. I am not that...
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    VHDL How to use TFP401 on a daughter card

    Hello, In my current project I am using these duo: LINK. Up to this point I was not using the receiver, and was generating the sync and display enable signals myself. Now, I am planning to implement the receiver to have a background video stream on which I will be painting stuff through the...
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    Text on Screen using FPGA

    Hello, My question is about finding the most suitable method to print text on DVI monitor using an Altera Cyclone 3 FPGA. In fact I am already doing this but I am not at all satisfied. I read the posts by echo47 and they are parallel to what I am using in my design right now. I hold rasterized...
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    [SOLVED] VHDL How to Design a Screen (Frame) Buffer

    Solved. The mistake was the address generation. Frame Buffer read address was generated in the blanking periods of the DVI interface whereas it should only be generated in the active region of the screen.
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    [SOLVED] VHDL How to Design a Screen (Frame) Buffer

    I am trying to solve this issue for hours, and still didnt make any progress. The screen is still scrolling after I played with the counter values, i.e. cycle times. I have rewritten most components in the project but they seem to work fine. I still think its a timing issue, but I just cant get...
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    [SOLVED] VHDL How to Design a Screen (Frame) Buffer

    library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity FrameBuffer is port ( data_a : in std_logic_vector(15 downto 0); data_b : in std_logic_vector(15 downto 0); addr_a : in natural range 0 to 80999; addr_b : in natural range...
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