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Recent content by ytass

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    Fully Differential Capacitor layout

    capacitor layout route Hi there, To get the ball rolling, I have drawn an AB BA capacitor structure. Unfortunately my routing is not common-centroid. Is there any way to make the routing symmetical? Please provide more feedback on my layout, thank you.
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    Differential Pair 2D Layout

    In my design I also require 2 x 2u/9u PMOS differential pair (CMFB circuit). Please find attached my layout for a single 2u/9u pair. I have arranged it as AB BA with A = B = 1u/9u device. Can someone please provide feedback on whether my layout is ok? I have placed a substrate connection near...
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    Fully Differential Capacitor layout

    differential capacitor Hi, I am designing a fully differential amplifier with capacitive feedback with a 32:1 capacitor ratio. I need the capacitors in common centroid. In addition each of the two signal paths should be the same. I have attached a picture of what I think the geometry should...
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    Long Width, 4:1 current mirror layout

    matching current mirrors width length As my application is for low level signals, should I place guard rings around all of my functional blocks, i.e., all diff pair, all current mirrors etc?
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    Long Width, 4:1 current mirror layout

    how current mirror layout can be draw JarryZhao, thank you very much for your suggested layout, this has helped me understand how to design long length current mirror ratio. Laglead, i use a W/L << 1 as my circuit is a low-power low-bandwidth (10kHz) amplifier. It is low-frequency because I...
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    Differential Pair 2D Layout

    Thanks everyone for your replies. So AB BA would have matching performance as good as ABBA BAAB ? Or is the reason that people use AB BA because the routing is easier? Are there any hard and fast rules for the routing of the drain and source connections for the AB BA structure?
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    Long Width, 4:1 current mirror layout

    current mirror layout Hi everyone, Most transistor layouts in the textbooks are only concerned with W/L > 1 layouts. For good matching, they use interdigitated fingers. For a current mirror layout, can anyone suggest a good layout topology if W1/L1 = 4/20 and W2/L2 = 1/20 ? I am not sure how...
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    Differential Pair 2D Layout

    What do you mean by quad structure?
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    Differential Pair 2D Layout

    Thanks for the reply, but with no explanation about the layout, it isn't too much help. The layout that yuo have provided is very complex and it is difficult to read all of the layers. Can you please provide more information, thank you.
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    Differential Pair 2D Layout

    Hi there, This is my first time doing a differential pair layout, and I am hoping to gain some helpful pointers. My partially complete differential pair is shown in the attachment (screenshot). I am using Cadence Virtuoso. My transistors are W/L = 56um/4um. I am using the 2D structure...
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    Matching of long transistors

    Hi rfsystem, Thanks for your reply, although I don't think you addressed my question at all. What I am asking is, are there good layout techniques for long length transistors, in particular, are there ways to layout long length current mirrors? The only reference I have for long length...
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    Matching of long transistors

    Hi there, I'm also doing an ota design with ultra low currents (400nA), and need some transistors with W/L = 1/50 to get my Veff = 0.2V. Does everyone recommend that I operate these current mirrors in subthreshold? But surely the device mismatch won't be good? Are there good long-length mosfet...
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    Cadence Virtuoso Edit Library

    artparameterintooldisplay Hi there, I have the NCSU Library installed. I want to add the parameters \'area\' and \'perimeter\' to the drop down list, as the technology that i am using expects these parameters. I opened to NCSU_Analog_Parts library and edited the code in artSimInfoCDF.att by...
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    How to test the CMRR of a fully differential amplifier?

    fully differential cmrr Can you please explain how to simulate CMRR for a fully differential op amp? I want to perform a Monte Carlo simulation and then select the worst case CMRR. How can I ensure that the simulation parameters are the same in my circuit for a given simulation run? Cheers.
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    Autozeroed amplifier aliased wideband noise

    Hi there again, Is there an experienced analog designer who can point me in the right direction? It would be much appreciated.
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