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Good tip ! I didn't know those circuits actually exists.
To run my tests I'm gonna use a component of this familly (Texas Instruments): "CDCLVC11xx 3.3-V and 2.5-V LVCMOS High-Performance Clock Buffer Family"
I'll keep you posted of the tests and solution I'll be choosing.
Hi,
The output signal of the FPGA internal PLL will be use to give the clock (100 MHz to 130 MHz) to 3 Analog to Digital Converters (AD9433).
The output level is 0 V / +5 V.
I don't know if there is any particular requirements using this ADC (Didn't see anything in the datasheet).
Thank you for...
Hello there,
I'm using the 10M08SCE144A7G FPGA.
In my design I need to give a clk input signal to 3 diferents Analog to Digital Converters. I'm thinking of using a PLL External Clock Output (signal PLL_L_CLKOUTp of the FPGA) to give the clock to these 3 converters.
There is only 1 output of...
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