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2 NMOS connected as current mirror with 1:5 ratio. 1 being the source side and 5 being the load side.
Question: which one has more contribution to the load and why?
My answer was the 1, or source side NMOS. Any noise will copy 5 times to the load.
The interviewer gave me a hint that the thermal...
Class A, max PAE 50%, 6dB back off means 1/4 of RF power, with same bias, DC power remain the same. So the efficiency become 50%/4.
Class B, biased on pinch off, so doesn't matter the lower RF power, it is still a class B, so the efficiency is still 78.5%.
This is an interview question I was...
Thanks vfone, can you explain why low impedance is desirable for low noise circuits?
1644786904
My understanding is for the same power, higher impedance has lower current . CMOS thermal noise is proportional to gm, and thus square rote of Id. so lower current is better for noise
yes, I totally understand this as I design LNA before. but I felt like this question is to test other general knowledge on receiver not only LNA, so I gave my above answer. looking back now I think this is a trick question, something like there are 10 birds on the tree, you shot one, how many left……
it was asked in this way, no more details. Initially I said if the source is 50 ohm, and the receiver input is a CMOS LNA, then step up. but that seems not satisfying the interviewer. so I guess this is a general question and gave the answers in my first post.
for receiver input matching, do you want to step up the impedance or step down, why?
my answer: step up. because 1. higher impedance lower current and thus less noise; 2. higher impedance can do filtering easier
I am not sure, am I right? what is the correct answer?
ideal class A and B PA, with 6dB backoff input power and same bias conditions, what are the efficiency?
my answer is
A: 50%/4=12.5%
B: 78.5%
am I right?
Thanks for your reply. Yes, adjusting the bias is a key tuning knob that we are using, but that is not the solution. The problem is the nulling point is lower in power comparing with the one with 2nd harmonic termination. Another problem is without harmonic termination, the ACLR AB hump at...
I am designing linear power amplifier for cell phone, all of our PAs (L/M/HB) need 2nd harmonic termination to get good linearity and PAE. Removing the 2nd harmonic termination degrades performance a lot no matter how we tune it. However I know that removing the harmonic termination while...
It is a high frequency transimpedance amplifier, input signal is 500MHz. and the input current signal is small.
How to generate and measure the input current signal?
thanks
+13.56 +card reader antenna pcb design
I did some simulation on ADS. I import the MOS model of IRF510 from international rectifier. After tuning, I got a efficiency of 83% out of the PA. The load is 5 Ohm.
Is my testing setup correct?
rfid reader schematic
Another quesiton:
We use class E PA because it can provide higher efficiency. But if the load is an inductor such as a coil antenna. Ideally it has no power loss at the load. In this case how to calculate the efficiency?
irf510 pspice
An RFID reader includes a transmitter and a receiver.
Yes L1 is not an RF chock. After I read some power amplifier design, I think this is a class E PA. L1 and the MOS drain capacitance (including C1) resonance at the operation frequency (13.56MHz).
But I still can not understand...
13.56mhz power amplifier
I found an application note from MicroChip about a 13.56MHz RFID reader reference design. I attached the schematic here. I have some questions:...
For the power amplifier, how to design the matching network? how to decide the component value?
In this PA design, the...
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