Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
In many applications, we need to connect our ASIC with a processor. Usually, these two systems (ASIC and processor) are asynchronous. How do we design a interface circuit for these two systems ?
When we want to implement a delay-line(2048 taps, 16bits for each taps), which one of the following design is better (small chip area / lower power consumption)?
1. Use shift register.
2. Use two port SRAM(1R/1W).
Since there is no "division" hardware in the ARM7 processor, is there any algorithm which can lower the CPU loading if we want to use the division operation ?
Question about USART
I use AT91 r40807 arm7 cpu. When I implement the interrupt-based usart driver, the system will crash occasionally. Does anyone encounter this problem before ? Could anyone offer usart driver ?
Re: GPS performance tests!
In practical, there are two case we need to care about : static test and dynamic test. In the static test, except for the C/o test and TTFF, the position accuracy is important--typically less than 25 meters CEP is need. In the dynamic test, sentivity of the GPS...
good vhdl styl
Writing a VHDL code is easy, but to write a GOOD and SYNTHESIBLE VHDL code is not trivial.
Is there any guide or example for a better VHDL coding style ??
vhdl max
Could any one tell me about how to write a VHDL code to find the max value of the one-byte input data. ( This input data will change as time goes by )
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
