Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: what is the input common range of the folded-cascoded OT
i think the upper limit is vdd-(2vov+vgs)=vdd-(3vov+vt)
but i am not sure what the lower limit is.
please tell me
can anyone tell me how can I simulate the SNR of a S/H circuit with Spice?
my input signal is a sine wave, but the output waveform is not sine wave again, so it is not correct to use .fft directly, need for your help. thank you!
can anyone tell me when SC CMFB is used in a fully differential amplifier, what is the best ratio between the CMFB bandwidth and differential bandwidth? thank you
i am sorry that i uploaded a poor figure last time, so i upload again now
can someone tell me why these six transistors are added? i mean, without them, the circuit will also have the same function. can the speed or precision be improved? thank you
1 and 2 are clock signals which are...
in sample and hold circuit. the OTA is not used during sampling, so, will the GBW and return ratio of the OTA during the sampling mode have any effect on the s/h?
and, if the load capacitor of the sample mode and hold mode are differnet (such as SC CMFB is added), what will happen?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.