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The up is input noted the net name to help analys.The output is like a AB class .Someother shematic is very complex.I think it is level shift for drive AB output stage,yes or no?The others schematic is drawing .
Net ct control the frequcy compensent.M5 M6's gate is to gnd.The power supply is...
thx for deba_fire's reply
the input signal frequency is about 2KHz,I want to use the switch capacitor amplifer
to implement the mathy opration. My question is there are double input signal.
the 1/1+LG is suitable for SISO, Vout=K3*(K1*Vin1+K2*Vin2) is DISO,which is two inputs and one output...
When i open the schematic ,i can't see any instance.It's noting on the window.I try to open other schematic,it also like that.
When i change to other user,i add the lib ,open the same schematic , i can see the instance.
what's wrong with the orignal user?
To design a mathy oparation for Vout=K3*(K1*Vin1+K2*Vin2),So i used three opa.If the final error less than 0.1%,how to calculate the three opas' accuracy,how to get the DC gain. THX!
The ideal opa is work well.I thinK the proble is OPA but not the switch or capacitor .
Tell us the frequency if switch and the OPA's gainband and settingtime!
Maybe the opa is not satable ,what is the PM?
Capacitor Mismatch
The ratio of 1C and 1C capacitors might have 0.1% error. But the ratio of 128C and 128C capacitors will have 0.01% error.
is it suit for the normal cmos technolygy?
Added after 9 minutes:
The SAR ADC is different from the Pipline ADC ,So the way for choosing the unit...
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