Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by ydlm42sj

  1. Y

    fix hold will reduce setup tns or increase setup tns? what about setup wns?

    fix hold will recude setup tns or increase setup tns? what about setup wns? fix hold will recude setup tns or increase setup tns? what about setup wns?
  2. Y

    Role of hvt cells in fixing noise

    While doing noise fixes, we change cells to a lower threshold voltage value, like from hvt to svt .
  3. Y

    timing analysis in digital circuits

    false path means that the circuit contains asynchronous logic.
  4. Y

    Help me in SOC encounter............

    i have the same problem :evil:

Part and Inventory Search

Top