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Recent content by yasonwang

  1. Y

    What's your opinion on CAD tools for Windows/Linux OS?

    Cad tools If memory is enough, not occupying swap area, the speed is good.
  2. Y

    Which metal layer is suitable for power routing around chip?

    Routing Power Wide metal on top Narrow metal on bottom
  3. Y

    what's "a Tiehi and Tielo gate" ?

    cmos tiehi cell TieHI/LO usually is one ESD protection diode preventing input poly oxide stroken by electro-static current.
  4. Y

    mostly used verification language in industries?

    SystemVerilog combines VERA and superlog. It is a successor from VERA.
  5. Y

    Where can I find some tutorial about tcl?

    search in google for tcl/tk.
  6. Y

    how to determine pin list

    Do you mean pin order? Or IO selection?
  7. Y

    how to install soc41_usr3_lnx86 in redhat-el-3?

    You just need to untar it and set path.
  8. Y

    Problem to generate SDF on A$tr0

    Only clock is defined, correct check arc can be generated, like setup/hold check.
  9. Y

    How to check if a cell has a reset pin in Design Compiler?

    Reset pin You can check the removal/recovery arc to pick out the reset pin.
  10. Y

    Looking for useful books/websites about physical design

    about physical design There are only some thumb rules.
  11. Y

    How to find the gate count

    For SOC Encounter, you only need to report equivalent gate count. That is easy and straightforward.
  12. Y

    VCS, NC-Verilog and Modelsim, which is the best simulator??

    NC is my prefered one.
  13. Y

    Error in modelsim when manipulating with floating point controller

    modelsim use expanded name check if package fpu_test is in library work. If so, you can try: library ieee, std, work; use ieee.... use .... ....
  14. Y

    Timing mismatch between SDF and RSPF

    Is timing difference from different clock domains? SDF represents worst timing arc, but rspf can be used by delay calculator to compute multiple timing arcs between two nodes, especially for crossing region of different clock domains. For STA, we only trust in rspf results.
  15. Y

    embeded chip from RTL to GDSII, synthesis

    floorplan FE or floorplan manager to do floorplan; IE to place block; SE to P&R; Voltagestorm or Arcadia to analyze power rail; Celtic to analyze crosstalk and electromigation;
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