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Recent content by yashjain

  1. Y

    Pipeline: For Loop comparing Module (VHDL)

    Hi, I just can't use a counter for it. Reason: The input is a serial data of 10 bits each. So, I can't pause the data. And we do not want to use a buffer type system. But something more of using shifter or small array based system.
  2. Y

    Pipeline: For Loop comparing Module (VHDL)

    Hi, sorry for the late reply. I´m trying to extract ancillary data based on their DID/SDID. Ancillarya data is found in video data, and is serial data. The ancillary data follows the protocol SMPTE 291M Format -> FLAG1 -> FLAG2 -> FLAG3 -> DID-> SDID -> DC ->UDW-> CS DID/SDID - DATA id DC ->...
  3. Y

    Pipeline: For Loop comparing Module (VHDL)

    Hi, Yes, I have to compare my input data(y_data) with multiple did values. And have a enable signal high as a flag to indicate a match. I think, a sequential process is a good option and I agree with your suggestion of multidimensional array. Also we need to delay the data behind the DID value...
  4. Y

    Pipeline: For Loop comparing Module (VHDL)

    Hi, Iḿ trying to compare 40 values from a memory array to my input data. If any of those 40 data matches to my input data I go to next state. I´m using a FOR LOOP for comparing the values in one clock cycle. But it limits my Fmax clock frequency. How do I write a pipeline based code to check...
  5. Y

    [SOLVED] Reading from a TXT file to a 2d array in vhdl

    Hi, Nope you are getting it all wrong. The code reads all the data in one line. That is TEXT FILE:- 000 3FF 311 322 3FF 000 111 222 Then the code would put all the values of first line in the array. And reads next line when your condition is true. I have declared size of my array cause...
  6. Y

    [SOLVED] Reading from a TXT file to a 2d array in vhdl

    HI, Thanks TrickyDicky for the help! your 1st option is what I have implemented. ANd now it all works. MY text file character format wasn't right, thus it wasn't reading right. When I debugged the code to output the data is string that is when I got to know it. So, If anyone who wants to read...
  7. Y

    [SOLVED] Reading from a TXT file to a 2d array in vhdl

    Yes, thats what Iḿ trying to do. Pre read in the text data into an array and output it in another process. If you refer to above codes, create_enable process is used for outputting the data. And data_count process is basically counting the no. of data in one line along with making an array to...
  8. Y

    [SOLVED] Reading from a TXT file to a 2d array in vhdl

    Yup, already did it, but same result. result array is formed of size 10. But, the flie remains close. Or even If I add a enf file loop, it doesn´t read values. type anc_array is array (0 to 9) of std_logic_vector(9 downto 0); begin data_count: process variable anc_line : line...
  9. Y

    [SOLVED] Reading from a TXT file to a 2d array in vhdl

    If I use this process :- data_count: process variable anc_line : line; variable anc_data : std_logic_vector(9 downto 0); variable data_available : boolean; -- variable result : anc_array(others=>(others=>'0')); begin file_open(file_anc, "file_anc.txt", read_mode)...
  10. Y

    [SOLVED] Reading from a TXT file to a 2d array in vhdl

    Thanks! saw that later. Bit more debugging and the testbench would be complete. For some reason my file doesn't open in the code. Spent countless iterations but it doesn't seem to open. architecture behaviour of tb_generic_anc_extractor is file file_anc : text...
  11. Y

    [SOLVED] Reading from a TXT file to a 2d array in vhdl

    HI, it worked. But, further down the code, Iḿ encountering an error relating to array. Iḿ trying to read one TEXT file line one by one at a particular point. So, I have made an array which would load all the data from the text file and then output the data at specific event. I'm using this...
  12. Y

    [SOLVED] Reading from a TXT file to a 2d array in vhdl

    read text file to make a serial output data vhdl HI, I'm trying to read data from a text file and ouput every hex value in the line serially for my test bench. The output waveform is very weird and it's skipping some values of the line. Also the data is not generated at the clock edge. Can...
  13. Y

    [SOLVED] Reading from a TXT file to a 2d array in vhdl

    Hi, I wanna read my text file to initialise an array of 2d. Iḿ using this in my test bench. signal stream_data : a2_std_logic_vector_type(39 downto 0)(6 downto 0)(9 downto 0); signal din_anc : std_logic_vector(9 downto 0); create_SDI_stream : process...
  14. Y

    generic ancillary data extractor and inserter

    EDIT:- I'm starting to work on an ancillary data extractor and inserter for 3G-SDI resolution for IP network. I've read some articles for the same:- https://core.ac.uk/download/pdf/143403310.pdf file:///C:/Users/Yash%20Jain/Downloads/Multiplexer_HDSD_draft%20(1).pdf...
  15. Y

    generic ancillary data extractor and inserter

    Hi, I'm working on an assignment to develop generic ancillary data system over IP network to be used in broadcasting TV station. Can someone help me out with the architecture and impementation?
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