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Recent content by yanzixuan

  1. Y

    how to use assert to verify the clock width in VHDL?

    I try this: assert rising_edge(clk_osc_C) and clk_osc_C'last_event >= 10 ns report "the width of clk_osc_C is too narrow" severity ERROR; bu failed, can any body give me some suggestion?
  2. Y

    How to force the DC to generation TIEHI and TIELO

    How to force the DC to generate TIEHI and TIELO Hi All, I'm working on a project and I encountered a problem. After systhesis, I check the gate-netlist and found that: some ports of sub-block are assign to be 1'b0, 1'b1. But in normal condition, it should be connected to TIEHI and TIELO block...
  3. Y

    how to get a clock timing constraint file for CTS.

    can design compiler do this work? bow
  4. Y

    Please help me of synthesised code simulation

    Hi poluekt, thank you for your replay ,I had used the command: report_constaint -all_violators and got such message: the design has no violated constraints
  5. Y

    Please help me of synthesised code simulation

    no. so I add sdf information, it's right now. Thank you. But I still wonder, why? I mean, the sdf just increase the net delay. whit out this, the timing performance should be better. bow
  6. Y

    Please help me of synthesised code simulation

    Hi All, I designed a counter ,and set clock constraint as follow: create_clock -period 8 -waveform {0 4} [get_ports clk] do compile and get the synthesised file for simulation. the timing report as follow([all_registers]) Point Incr Path...
  7. Y

    Please help me about the tcl command trick of Design compiler

    In one block, all registers are all driven by "clk", but some registers(Type A) are control by "clk_en" by Enable pin. Some is there any dc command to find all the (type A) registers? bow
  8. Y

    How to learn synthesis

    Hi All: I'm front end designed. recently, I became to learn synthesis. do you guys have any suggestions or tricks? Thank you.8-)
  9. Y

    I need one help in my project please help me

    you must add ACTEL library in you design and do this again. But if you are using Xilinx, you need re-compile your RTL level codes by using ISE.
  10. Y

    how to use % operator in verilog

    Re: verilog modulo operator It's not synthesizable is your second operand is not 2. you need design by hand.
  11. Y

    How to create a sine wave with verilog ?

    Re: verilog sine wave 1 Lookup table 2 cordic
  12. Y

    How to calculate power of a circuit implimented on Virtex-5

    there is a power analysis tool which is includes in ISE.
  13. Y

    [SOLVED] help ! random func in systemverilog

    I thought it should be like this: module xyz(); reg [31:0] addrmem [31:0] initial begin for ( i=0 ; i<32 ; i++) begin addrmem[i] = $random(); end end endmodule
  14. Y

    I2C interrupt in arm microcontroller

    have you add your I2C ISR to your startup file??

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